URSI 2007, XXII Simposium Nacional de la Unión Científica Internacional de Radio, La Laguna
This paper shows the implementation in a digital
signal processor (DSP or FPGA) of a Digital Adaptive
Predistorter (DAPD) for power amplifier (PA) linearization
based on a Nonlinear Autoregressive Moving Average
(NARMA) structure. The distinctive characteristic of this
DAPD is its straightforward deduction from the NARMA PA
model, without the need of using an indirect learning approach
to identify the DAPD function. The DAPD itself presents a
NARMA structure, and hence it can be quickly implemented by
means of Look-Up Tables (LUTs). WCDMA modulated signals,
collected from a 3-stage LDMOS class-AB power amplifier,
with a maximum output power of 48 dBm CW have been used
to validate the linearizer performance. The developed DSP and
FPGA based platform for prototyping digital predistortion
linearizers eases the process of meeting transmission linearity
requirements, depending of the degree of impairments added by
the transmitter chain, and enables a quick migration between
different DAPD schemes. Details on the internal DAPD
organization and abilities are provided, giving an insight on
actual development scenarios of predistorter systems
considering memory effects. Experimental results obtained
from the linearization of a 10 W class-AB LDMOS amplifier (2
GHz band) are provided.
; Bertran Albertí, Eduard; Berenguer i Sau, Jordi
