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dc.contributor.authorLeyva-Santes, Neiel
dc.contributor.authorPérez Gallardo, Iván 
dc.contributor.authorHernández-Calderón, César A.
dc.contributor.authorVallejo Gutiérrez, Enrique 
dc.contributor.authorMoretó, Miquel
dc.contributor.authorBeivide Palacio, Julio Ramón 
dc.contributor.authorRamírez-Salinas, Marco A.
dc.contributor.authorVilla-Vargas, Luis A.
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2020-03-30T13:48:40Z
dc.date.available2020-03-30T13:48:40Z
dc.date.issued2019
dc.identifier.issn1865-0929
dc.identifier.urihttp://hdl.handle.net/10902/18431
dc.description.abstractCurrent compute-intensive applications largely exceed the resources of single-core processors. To face this problem, multi-core processors along with parallel computing techniques have become a solution to increase the computational performance. Likewise, multi-processors are fundamental to support new technologies and new science applications challenges. A specific objective of the Lagarto project developed at the National Polytechnic Institute of Mexico is to generate an ecosystem of high-performance processors for the industry and HPC in Mexico, supporting new technologies and scientific applications. This work presents the first approach of the Lagarto project to the design of multi-core processors and the research challenges to build an infrastructure that allows the flagship core of the Lagarto project to scale to multi- and many-cores. Using the OpenPiton platform with the Ariane RISC-V core, a functional tile has been built, integrating a Lagarto I core with memory coherence that executes atomic instructions, and a NoC that allows scaling the project to many-core versions. This work represents the initial state of the design of mexican multi-and many-cores processors.es_ES
dc.format.extent14 p.es_ES
dc.language.isoenges_ES
dc.publisherSpringer Verlages_ES
dc.rights© Springer. This is a post-peer-review, pre-copyedit version of an article published in Communications in Computer and Information Science. The final authenticated version is available online at: https://doi.org/10.1007/978-3-030-38043-4_20es_ES
dc.sourceCCIS, volume 1151, pp 237-248es_ES
dc.subject.otherMulti- and Many -corees_ES
dc.subject.otherMultiprocessors RISC-Ves_ES
dc.subject.otherInterconnection networkses_ES
dc.titleLagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chipes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1007/978-3-030-38043-4_20es_ES
dc.rights.accessRightsopenAccesses_ES
dc.type.versionacceptedVersiones_ES


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