Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip
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AuthorLeyva-Santes, Neiel; Pérez Gallardo, Iván; Hernández-Calderón, César A.; Vallejo Gutiérrez, Enrique; Moretó, Miquel; Beivide Palacio, Julio Ramón; Ramírez-Salinas, Marco A.; Villa-Vargas, Luis A.
© Springer. This is a post-peer-review, pre-copyedit version of an article published in Communications in Computer and Information Science. The final authenticated version is available online at: https://doi.org/10.1007/978-3-030-38043-4_20
CCIS, volume 1151, pp 237-248
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Multi- and Many -core
Current compute-intensive applications largely exceed the resources of single-core processors. To face this problem, multi-core processors along with parallel computing techniques have become a solution to increase the computational performance. Likewise, multi-processors are fundamental to support new technologies and new science applications challenges. A specific objective of the Lagarto project developed at the National Polytechnic Institute of Mexico is to generate an ecosystem of high-performance processors for the industry and HPC in Mexico, supporting new technologies and scientific applications. This work presents the first approach of the Lagarto project to the design of multi-core processors and the research challenges to build an infrastructure that allows the flagship core of the Lagarto project to scale to multi- and many-cores. Using the OpenPiton platform with the Ariane RISC-V core, a functional tile has been built, integrating a Lagarto I core with memory coherence that executes atomic instructions, and a NoC that allows scaling the project to many-core versions. This work represents the initial state of the design of mexican multi-and many-cores processors.
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