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dc.contributor.authorLamo Anuarbe, Paula
dc.contributor.authorLópez Vidal, Felipe 
dc.contributor.authorPigazo López, Alberto 
dc.contributor.authorAzcondo Sánchez, Francisco Javier 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2018-05-09T11:30:16Z
dc.date.available2018-05-09T11:30:16Z
dc.date.issued2017-05
dc.identifier.issn0885-8993
dc.identifier.issn1941-0107
dc.identifier.urihttp://hdl.handle.net/10902/13660
dc.description.abstractSynchronization with the utility voltage is naturally carried out by a diode bridge stage in single-phase active rectifiers, while an active synchronization is included in the control algorithms applied to modern bridgeless topologies. Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The phase-locked-loop (PLL) circuits employed in single-phase ac-dc converters are reviewed and a new digital PLL algorithm, based on the synchronous reference frame, is proposed. It is implemented in a field-programmable gate array to utilize the parallelism and superior time resolution. Considering a restricted frequency variation of the line voltage around the central frequency, the orthogonal signal is obtained by a discrete differential operator designed to ensure unity gain at the central frequency. Its performance, including the memory and computational cost, versus previously consolidated algorithms implemented in the same device is analyzed. Simulations and experimental results prove its suitable behavior in steady state at different line frequencies and under line voltage and frequency transients.es_ES
dc.format.extent11 p.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineers Inc.es_ES
dc.rights© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other workses_ES
dc.sourceIEEE Transactions on Power Electronics, 2017, 32(5), 3959-3969es_ES
dc.titleAn Efficient FPGA Implementation of a Quadrature Signal-Generation Subsystem in SRF PLLs in Single-Phase PFCses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherVersionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7494977es_ES
dc.rights.accessRightsopenAccesses_ES
dc.identifier.DOI10.1109/TPEL.2016.2582534
dc.type.versionacceptedVersiones_ES


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