Two-Sample PLL With Harmonic Filtering Capability Applicable to Single-Phase Grid-Connected Converters

The two-sample phase locked loop (2S PLL) in single-phase digitally controlled grid-connected power converters provide synchronization with a minimal computational burden. However, the distortion of the grid voltage deteriorates the performance of the 2S quadrature signal generator. To solve this issue, this article introduces a harmonic filtering (HF) structure based on observers of the input voltage for the fundamental and selected harmonics. The stability and sensitivity of the 2S PLL with HF is analyzed. In comparison with second-order generalized integrator (SOGI)-based HF, the observers provide a narrower bandpass, and the subsequent deterioration of the response time is compensated by adapting the filter gains dynamically. The results obtained, both in simulation and experimentally, validate the proposal and compare its performance with other widely adopted PLLs providing harmonic rejection capability. The computational burden is analyzed and in the case of the proposals depends on the number of observers and the use or not of the adaptive strategy based on steepest descent.


I. INTRODUCTION
With the increasing penetration of grid-connected power converters, the requirements imposed by international standards and grid codes to their operation as frontends for both distributed energy resources (DER) and loads have increased. Among other functionalities, controllers in power converters must consider their effects on the local grid and contribute to the proper operation of the overall power system, i.e. by adjusting the power factor [1] and the dynamic response [2], which becomes more challenging in the case of disturbances and transients [3], [4]. One of the key elements to perform these tasks is the synchronization subsystem, which must be able to track the grid voltage at the converter connection point and maintain that synchronization even while electrical disturbances occur.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. grid-connected converters, the zero-crossing detection is a simple open-loop synchronization method, but very sensitive to the harmonic distortion and phase noise [9]. In such operation conditions, a closed-loop synchronization system is preferred and the PLL is commonly used [10]- [12] to track the phase of the fundamental component of the grid voltage. The phase detector (PD) and the loop filter (LF) must reject the harmonic components, which is more difficult in the case of single-phase PLLs based on the Park transform as the PD requires a quadrature signal generator (QSG), and the presence of harmonic distortion and frequency variations may deteriorate its performance. From the point of view of the PLL structure, different strategies focused on the modification of the QSG have been proposed to address these issues, as reported in [13]. The most significant being the concept of Delayed Signal Cancellation (DSC) [14]- [23] and moving average filters (MAFs) [21]- [24]. The strategies proposed for the harmonic elimination in the synchronously rotating reference frame (SRF) can also be classified in open-and closed-loop. The open-loop methods cover proposals based on DSC, MAF, second order generalized integrators (SOGIs) [25]- [29], filtering [30]- [32], pre-processed algorithms [32], fast Fourier transform (FFT) [33], sliding discrete Fourier transform (SDFT) [34], recursive discrete Fourier transform (RDFT) [35]- [37] and sliding-Goertzel-transform [38], [39]. Considering the harmonic elimination precision, these strategies may present large error if the grid contains other disturbances not contemplated in the design, such as grid frequency variation. This issue is overcome by adopting a closed-loop strategy based on multi-harmonic decoupling cell (MDC) and multi-harmonic SRF filtering (MSF) [39]. Enhanced structures [40], notch type adaptive filters [41], [42], observers of the frequencies of interest are proposed in the rotating reference frame (RRF) [43] and in the SRF [44] or selective harmonics elimination (SHE) methods [45], [46].
Following this line of achieving enough accuracy and low computational burden PLLs based on the Park transform, the 2S PLL, presented in [47], has a QSG that only requires a buffer for two samples (Fig. 1). This QSG considers a restricted frequency variation of the line voltage around the central frequency and utilizes the signal variation within three consecutive sampling periods to generate the in-quadrature signal. A drawback of this approach is the low immunity to voltage harmonic distortion. The digital implementation of the 2S PLL proposed in [48] is aimed at minimizing the computational burden of the 2S PLL for implementation in a field-programmable gate array (FPGA) but it does not improve its harmonic filtering capability.
Since the sensitivity to the voltage harmonic distortion is a handicap in the 2S PLL, this paper proposes to include an adaptive filter structure with minimal computational burden. The proposal is based on disturbance observers tuned at the frequency components of interest (up to the seventh harmonic) and using a closed-loop structure. The operating principles of the proposed filtering strategy and the assessment of its computational burden are also provided in this paper. Finally, the proposal is evaluated with simulations and experimentally. The paper is organized as follows. Section II compares the architecture of the proposed 2S PLL with adaptive harmonic filtering capacity. In Section III, the performance of the proposed PLL is compared with the SOGI PLL by simulation, while in Section IV, the comparison is carried out experimentally. In both sections, harmonically distorted grid voltages and fundamental frequency variations. Conclusions evaluating the applicability of the proposal to bidirectional H-bridge are finally provided.

CAPACITY
In order to filter out the voltage harmonic distortion, an adaptive filtering structure is proposed, as shown in Fig. 1. Each block H i constitutes an observer of each i th frequency component of interest in the grid voltage, i.e. fundamental plus 3 rd to 7 th odd harmonics and, the observed i th component at the sampling interval k, o i,k , is, then, estimated from the error signal, e k . The contribution of each observer H i to minimizing e k is balanced through the gains K i . By zeroing the error signal e k , the values α i,k are estimated and α 1,k is used as the PLL input, which makes the proposed filtering structure useful to other QSGs than the 2S.
From Fig. 1, the obtained closed-loop equation is the summation collects the contribution of the fundamental and all the harmonic components relevant for filtering purposes. From (1), each observer H i has to result in a resonance at the i th frequency, which nulls e k in steady state.
Moreover, the transfer function H i relates the scaled signal of the grid voltage at the frequency of interest, o i,k , and the overall error signal due to the set of observers, e k , and, if the error signal is zero, each product K i H i tracks the i th frequency component of the grid voltage without error. To achieve this, a high gain, without phase displacement, is required. Moreover, to avoid interferences between observers, each observer must exhibit a relatively low gain at frequency orders different than i, and, then, the following configuration is proposed for H i where H' i (z -1 ) estimates the current value of the i th component from the previous samples. In order to evaluate H' i (z -1 ), the phasorial representation of the i th component in a stationary reference frame at the sampling interval k is considered: where, A i,k is the amplitude, ω is the fundamental frequency of the grid, and T s is the sampling period. Then, and assuming that amplitude and grid frequency variations are slow enough, the estimated in-phase projection at instant k+1, α i,k+1 , is obtained from where N = 2π/ωT s is provided by the PLL. Substituting (3) and (4), into (5) results in that, in filter form, is rewritten as whereα i is the estimation of α i and N is provided by the PLL. Then, with H i z −1 = z −1 G i z −1 and using (2), Figure 2.a shows the Bode diagram of H 1 , according to (8), with three different T s , where it is observed that the design requirements are accomplished and |H 1 (ω 1 ) | → ∞ . Other observers, at different sampling frequencies, perform similarly and result in |H i (ω i ) | → ∞ . Figure 2.b shows the equivalent Bode diagram of the SOGI (whose transfer function is H SOGI which have a band-pass filter characteristic.

A. Adaptive Filter Gains
The filter gains are adjusted adaptively by means of a gradient descent method [49]. From the block diagram in Fig.  1, the instantaneous error of the HF is used to evaluate the continuous cost function, J, to be minimized. Then, in terms of the HF input signal and the contribution of each i th filter tap, which is adjusted through K i , the cost function becomes where the contribution of each observer is considered. Then, the gains are adjusted by [47] including the proposed filter of the harmonic distortion of the grid voltage.
which is discretized as where η is the learning rate and must be selected to balance the convergence rate and the steady-state error of the harmonic filter. More details about the procedure for selecting the most appropriate η values can be found in [49]- [51]. From these considerations and (11), the selection of a suitable parameter η would depend on each product e k o i,k and then, it is normalized here by means of resulting in the iterative rule where and µ ∈ R + and is selected to ensure the filter stability and convergence.
Since the performance of gradient descent methods can be sensitive to the initial conditions [51], [52], an initial guess for each K i considers that the filter error in (1) equals zero for the selected frequency components. That is, |H i (ω i ) | → ∞ forces that the contribution of each i th component results in null error.
As an example, let's consider the fundamental plus the 3 rd and 5 th harmonics. Then, the structure in Fig. 1, without gain adaptation, is reduced to the scheme shown in Fig. 3, with K 1,0 , K 3,0 and K 5,0 as filter gains. The resonant sections in H 3 and H 5, within the 3 rd and 5 th inner loops, must cancel the voltage harmonic distortion at these frequencies.
Simultaneously, other control targets of the control loops are i) minimize the attenuation below the resonant frequency and ii) minimize the deviation of the relative harmonic phase. K 3,0 , and K 5,0 must be increased to achieve i) while, for ii), K 3,0 , and K 5,0 must decrease. The tuning procedure starts with the inner loop, resulting in K 5,0 = 4.51e-3. Then, considering the closed loop transfer function T 5 = 1/(1+K 5 H 5 ) and the next filtering stage, H 3 , it results in K 3,0 = 2.73e-3. Finally, the value K 1,0 must compensate for the attenuation due to H 3 and H 5 . By increasing K 1,0 , the magnitude of the frequency response flattens at the fundamental but the resonance peaks, due to H 3 and H 5 and the DC component are not filtered out. Moreover, the time response becomes slower, so K 1,0 must be selected to achieve a fast-enough time response compatible with the required zero gain and zero phase at the fundamental. The constant, K 1,0 is selected as 6.79e-3. If frequency variations are likely to occur while starting the gain adaptation algorithm, a less restrictive approach must be adopted, and this value can be increased to compensate for. Following the design example, other observers, at higher harmonic orders, can be included within the filtering structure.

B. Filter Stability
For simplicity sake, the filter stability is analyzed by considering two harmonic filter taps, at 3 rd and 5 th harmonics, but it can be extended to other sets of selected harmonics. The sampling frequency is large enough to ensure that variations of N = 2π/ωT s around the central frequency of the PLL are limited and the ratio i/N is low enough. Moreover, the values K i , despite of being dynamically updated in Fig. 1, are limited.
Then, the filter transfer function, G L z −1 , and the characteristic polynomial, P L z −1 , are defined as and By applying the Jury criterion, the following necessary conditions are achieved, which are valid under the assumption i/N small enough: i={1,3,5} The first condition is accomplished by using K i ∈ R + , and, from the second one, K i ∈ (0, 2), independently of the selected harmonic orders. The initial values given in Section II.A verify this condition.

C. Sensitivity to N
The sensitivity of the closed loop transfer function T(s,N) to N parameter variations are evaluated by where and, using z=e sTs within (7): which results in (20). If T s is small enough for the selected maximum harmonic order of the filter, then the following approximations can be used.
and, then, where, considering a certain set of harmonic orders and limiting the applied K i values to maintain the stability (see Section II.B), the sensitivity of the closed loop transfer function to the parameter N is S T N (s, N ) ∝ 1 N 2 and, hence, , which can be kept low enough by selecting the proper harmonic orders and the sampling frequency used.

III. SIMULATION RESULTS
The proposed harmonic filter (HF) stages, considering 3 rd , 5 th and 7 th voltage harmonics (H 1 plus H 3 , H 5 and H 7 blocks), using both versions, the non-adaptive (µ=0 and K 1 =1.98e-3, K 3 =1.51e-4, K 5 =3.9e-4, K 7 =3.74e-4) and adaptive (relatively slow, µ=5e − 5, and relatively fast, µ=5e − 3), have been incorporated to the 2S PLL and evaluated by means of a Monte Carlo (MC) tests using Matlab/Simulink R . While focusing on evaluating the harmonic rejection capability provided to the 2S PLL, a performance comparison with widely adopted PLLs providing harmonic rejection capability is also given: the same tests and conditions have been run with the 2S PLL without prefiltering stage [47], the SOGI PLL [4], [51], with crossover frequency set to 1.8 Hz, the Multi SOGI (MSOGI) PLL [52], with SOGIs at the fundamental, 3 rd , 5 th and 7 th , the DSC PLL [53], with rotations at 2π/8, 2π/16 and 2π/32 radians, and the MAF PLL [54] with constant window length equal to one grid period at the nominal grid frequency. The same phase detector, loop filter (T settling =0.6 s [4]) and oscillator are used in all the cases. The sampling time, T s , is 156.25 µs.
All the MC tests consider harmonically distorted grid voltages, within the limits stablished in EN 50160 [55], interharmonics and other effects due to the measure chain, such as noise and DC components. A total of 171 simulation conditions are generated through Latin Hypercube Sampling (LHS), which allows the representative number of MC tests to be reduced. Voltage harmonic combinations, with orders from 2 nd to 50 th and amplitudes within the individual and collective limits in EN 50160 (VTHD ≤ 8 % ), are considered. Results are presented according to a uniform probability density function (PDF). The nominal grid frequency changes in the test following a normal PDF, according the EN 50160 limits. The interharmonics within DC and 100 Hz are also included in the LHS by means of a uniform PDF and individual peak value of the nominal grid voltage equal to 0.5 % .
The resulting PDFs for the measured mean phase error (θ e ) in steady state are shown in Fig. 4 Fig. 4.b but it must be considered that only four, H 1 , H 3 H 5 and H 7 , filtering blocks have been used in the 2S PLLs with HF. If more blocks were included, despite of increasing the computational burden, this ripple ( Fig. 4.b) and the average error ( Fig. 4.a) would be further reduced. Within the set of widely adopted PLLs, the MSOGI shows the worst phase ripple results (the median is 0.  Fig. 6.b, where small performance differences are appreciated. In terms of response times, the best performer is the 2S PLL with fast µ = 5e − 3) adaptive HF, achieving 882.891ms and 298.721ms as median and variance, respectively. The worst performer is the MSOGI PLL (median and variance equal 1076.094ms and 684.313ms, respectively). In comparison with frequency ramps, where the best performer 2S PLL is the slow adaptive version, sudden frequency changes are best managed by a more aggressive adaptive action. Figure 7 shows the obtained results in the case of phase  Fig. 7.a and 7.b, respectively. The overshoots (Fig. 7.a)  ) and the response times ( Fig. 7.b) differ slightly. Within the 2S PLLs with HF, the fast adaptive version (µ = 5e − 3) shows the fastest median (719.609ms) but, as in the case of the slow adaptive version, both are less consistent than the non-adaptive HF. As in the case of frequency jumps, speeding up the steepest descent strategy, the PLL performs better. MSOGI and SOGI PLLs are the best performers in this test, achieving 589.688ms and 590.781ms medians, and 11.293ms and 10.656ms variances, respectively. T  M  SOGI  4  3  0  2  MSOGI  1+6F  4F  0  2F  MAF  10 Fig. 8.a. The performance of the 2S PLL without HF is equivalent to the one observed in the steady-state test (Fig. 4.b). By including the proposed HF stage, the overshoot increases, becoming worst without adaptation capability. Within all the analyzed PLLs with HF capability, best performers are SOGI, DSC and MAF PLLs, with overshoot medians in the range [0.523 o , 0.563 o ]. The PDFs of the measured response times are shown in Fig. 8.b. The largest median corresponds to the 2S PLL with slow adaptive HF, which can be improved by speeding up the steepest descent algorithm. Overall, the PLLs with SOGI, MSOGI, DSC and MAF perform better than 2S PLLs in presence of voltage dips. Table 2 summarizes the number of operations and memory units required for the digital implementation of the proposed adaptive filtering stage and the 2S QSG, described in Section II. For comparison purposes, equivalent PLL blocks in other single-phase PLLs with harmonic filtering capability are also evaluated. The 2S QSG, without harmonic filtering structure, requires the fewest operations. By including the harmonic filtering structure, the number of operations and memory units increases depending on F , i.e. the number of voltage harmonics to be filtered out. The DSC and MAF QSGs require a number of data memory units that depends on N and the trigonometric functions. It must be also considered that if the set of harmonic orders is restricted [53], the number of rotation stages of the DSC QSG is reduced accordingly. The difference between the resources in the 2S QSG with non-adaptive and adaptive HF is due to the steepest descent block shown in Fig.  1, included in the adaptive HF and the procedure to adjust the frequency of each observer as a function of N . The SOGI QSG exhibits similar computational burden than the 2S PLL without filtering stage, while the MSOGI performs similarly than the 2S QSG with non-adaptive HF.

IV. EXPERIMENTAL RESULTS
The proposed 2S PLL with harmonic filter is evaluated experimentally using a Full-Bridge AC-DC bidirectional con- verter working as an active rectifier. A 500 Ω 320W DC load is feed through an H-bridge, the output voltage, v dc , and the input current, i g , are filtered out by means of the output capacitor C (500 uF ) and the input LCL filter (L g = 1 mH, L c = 2 mH, C f = 7 uF ) respectively. A programmable HP 6841A power source is used to emulate the grid voltages, v g , for different operation conditions. The digital controller is implemented in a dSpace DS1103, at f sw = 6.4 kHz, providing the gate signals g x by means of a unipolar PWM strategy which is used to synchronize the signal acquisition. Hall sensors are used to sense v g , i g and v dc . Signal conditioning and antialiasing filtering (4 th -order multiple-feedback Butterworth) stages are included.
The digital controller consists of a DC voltage controller, the synchronization subsystem and the current controller. The sensed v dc signal is compared to the reference one (v * dc = 400V ) and the error signal is applied to a PI controller (K pc =24e − 3 and K ic =11e3) which outputs the amplitude of the grid current (I * g ) required to feed the R load at v *  . Different synchronization strategies can be tested and, in order to achieve unity power factor, they must provide the signal sin (ωt + φ 0 ) , in-phase with the fundamental of v g . Then, the reference input current i * g is obtained by multiplying I * g and sin (ωt + φ 0 ) . The reference current i * g is compared to the actual i g and the error signal is provided to a proportional-resonant controller (K pc = 6, K ic = 1e-3) plus a harmonic controller at 3 rd , 5 th and 7 th (with gains K 3 = K 5 = K 7 = 200) to compensate for the grid harmonic distortion. The resonance frequency is adjusted dynamically using the value provided by the PLL and all the integral blocks include an anti-windup functionality. The characteristics of each control subsystem have been selected to decouple the effect of other control loops and achieve a good performance during frequency step tests. More details about these controllers can be found in [4]. Three 2S PLLs, with adaptive HF, non-adaptive and without HF, are compared to the SOGI PLL. The configurations of other subsystems within the digital controller are maintained across the tests.
The grid frequency ω exhibits ripple, which moves the resonant peak of the resonant and the harmonic controllers around the actual ω. This effect is mitigated by designing the PLLs to limit the peak-to-peak ripple 20 mHz at 50 Hz. With this objective, the loop filter of the 2S PLL with adaptive HF is tuned following the procedure in [4], [47], resulting in a settling time, T set = 0.6 s. This settling time is also used in the 2S PLL versions with the non-adaptive HF and without filter. The SOGI PLL is tuned according to the procedure in [52] and, then, the selected crossover frequency of the SOGI PLL is set to 1.8 Hz. The results obtained are shown in Fig. 9. The tests conditions are frequency steps from 49 Hz to 51 Hz and harmonically distorted grid voltages (2% , 3% and 2% of the 3 rd , 5 th and 7 th harmonic, respectively). Steady state, before and after the frequency step, and transient responses are evaluated. The best steady state performance (PF = 0.994) is achieved with the SOGI PLL ( Fig. 9.d). Close to these values, the 2S PLL with adaptive HF ( Fig.  9.a), results in PF = 0.993 and PF = 0.992 at 51 Hz and 49 Hz, respectively. The 2S PLL with non-adaptive HF ( Fig.  9.b) reaches the performance of the adaptive version at 51 Hz but, at 49 Hz, the PF becomes the worst (P F = 0.978). Due to the tuning procedure followed, all the three PLLs results in equivalent frequency ripples. Maintaining the same settling time in the 2S PLL without harmonic filter results in a higher frequency ripple (Fig. 9.c), which is due to the harmonic distortion passing through the QSG. However, it achieves a relatively high PF at 49 Hz (PF = 0.987).
Transient responses show that, in all the evaluated PLLs, the performance is dominated by the loop filter dynamics. The fastest response is achieved with the 2S PLL without harmonic filter ( Fig. 9.c), resulting in a 214 ms transient and a line current peak of 1.1 A over the normal operation conditions. 2S PLLs with harmonic filters result in similar transient responses, with the adaptive version ( Fig. 9.a) performing better, 18 ms faster and 0.1 A lower peak current, than the non-adaptive version ( Fig. 9.b). In the case of the SOGI PLL, the applied crossover frequency results in the slowest response time (582 ms), the greatest peak current variation (2.5 A) and a frequency peak of +0.8 Hz over the real grid frequency. This behavior can be improved by increasing the crossover frequency, but the frequency ripple would increase accordingly.

V. CONCLUSION
A new harmonic filtering structure has been embedded in the 2S-PLL synchronization circuit, whose original version lacks harmonic filtering capacity. The proposed harmonic filtering is based on observers at each frequency of interest in the grid voltage and each observer is built following the 2S approach. Two versions of this filtering stage have been proposed: non-adaptive and adaptive. The adaptive version adjusts the filter gains dynamically leveraging the steepest descent method, improving the 2S PLL performance in the case of grid voltage events and transients, and increasing the consistency of the 2S PLL performance across different grid conditions. In Fig. 9: Line current and voltage waveforms due to a frequency step (2 Hz) and harmonically distorted grid voltage (2% , 3% and 2% of the 3 rd , 5 th and 7 th harmonic, respectively) with a) 2S PLL with adaptive HF, b) 2S PLL with non-adapttive harmonic filtering, c) 2S PLL without harmonic filtering and d) SOGI PLL f crossover = 1.78 Hz. PLL frequency: f PLL , dark blue. Grid voltage, v g , magenta. Line current, i g , light green.
comparison to other single-phase PLLs with harmonic filtering capability, such as SOGI and MSOGI, the proposal achieves a similar, or superior, performance. The computational burden of the 2S-PLL is higher than other commonly used structures it has been compared to when embedding the harmonic filtering stage, particularly in the adaptive version. However, when the grid harmonic distortion is due to a reduced set of specific harmonics, the proposed approach allows to filter out them while the associated computational burden is kept in the size of other single-phase PLLs counterparts with harmonic filtering capability. By comparing the proposed PLLs with the most similar structures, the MSOGI and 2S PLL with the non-adaptive filtering stage, it performs better in the case of grid frequency ramps and jumps, while the associated computational burdens are similar.