Power Quality Enhancement in Residential Smart Grids Through Power Factor Correction Stages

The proliferation of nonlinear loads and the increasing penetration of distributed energy resources in medium-voltage (MV) and low-voltage (LV) distribution grids make it more difficult to maintain the power quality levels in residential electrical grids, especially in the case of weak grids. Most household appliances contain a conventional power factor corrector (PFC) rectifier, which maximizes the load power factor (<inline-formula><tex-math notation="LaTeX">$\text{PF}$</tex-math></inline-formula>) but does not contribute to the regulation of the voltage total harmonic distortion (<inline-formula><tex-math notation="LaTeX">$\text{THD}_V$</tex-math></inline-formula>) in residential electrical grids. This paper proposes a modification for PFC controllers by adapting the operation mode depending on the measured <inline-formula><tex-math notation="LaTeX">$\text{THD}_V$</tex-math></inline-formula>. As a result, the PFCs operate either in a low current total harmonic distortion (<inline-formula><tex-math notation="LaTeX">$\text{THD}_I$</tex-math></inline-formula>) mode or in the conventional resistor emulator mode and contribute to the regulation of the <inline-formula><tex-math notation="LaTeX">$\text{THD}_V$</tex-math></inline-formula> and the <inline-formula><tex-math notation="LaTeX">$\text{PF}$</tex-math></inline-formula> at the distribution feeders. To prove the concept, the modification is applied to a current sensorless nonlinear controller applied to a single-phase boost rectifier. Experimental results show its performance in a PFC front-end stage operating in the continuous conduction mode connected to the grid with different <inline-formula><tex-math notation="LaTeX">$\text{THD}_V$</tex-math></inline-formula>.


I. INTRODUCTION
H ARMONIC limits in AC electrical grids are established by international standards and grid codes in order to ensure an efficient and proper operation of the subsystems and equipment connected to the grid, i.e. generators, loads and storage systems.The IEEE 519-2014 recommended practice and requirements for harmonic control in electric power systems [1] defines the limits on specific harmonics as well as on the current Total Harmonic Distortion (T HD I ) and the current Total Demand Distortion (T DD).Voltage and current harmonic distortion levels in electrical distribution systems are closely related, and the recommended T HD V limits in distribution feeder tap points are likely exceeded if highly nonlinear loads are connected [2].Exceeding voltage or current harmonic limits reduces the overall efficiency and might produce critical faults in weak or critical Electrical Power Systems (EPS).Among others, harmonic distortion causes heating of induction motors [3], accelerated aging of insulation [4] and harmonic resonances in capacitors for reactive power compensation [5].Moreover, the harmonic distortion might affect the normal operation of medical equipment [6], [7] and distribution transformers in residential areas might suffer excessive loading, contributing to accelerate their aging [8].
The voltage harmonic distortion is mainly due to background harmonic sources, but residential loads contribute to increase the T HD V , especially at 3 rd , 11 th and 13 th harmonics [9].The effects of harmonics in residential areas are attenuated applying local or wide area mitigation approaches.Local ones are employed at the load or Distributed Energy Resource (DER) side, i.e. distributed generation and storage active front-ends, operated as adjustable harmonic impedances [10], [11] or including active power filter functionalities [12].Wide area mitigation strategies are based on the coordination of local solutions, i.e. assigning compensation priorities to DERs [13].The T HD V is improved by means of a droopbased approach [14], adjusting the equivalent DER admittance [15] or the deployment of distributed low-power low-voltage equipment for current harmonic filtering [16].The integration of mitigation equipment at distribution feeder level, i.e. hybrid active power filters, also contributes to increasing the P F and mitigating the effect of voltage disturbances on household appliances [17]- [19].The compensation capability and availability using DERs is limited by their nominal rating, i.e. the LCL filter characteristics [20], and the operation mode, i.e. reactive power compensation [21], respectively.Dedicated local filtering solutions require the integration of additional equipment, increasing the overall cost, and involve a previous analysis of their impact on the grid [16], e.g.resonances in passive filters.Moreover, coordination of local solutions would require communications that increase the deployment complexity.In contrast, this manuscript proposes a local load side approach, with no extra hardware cost, achieved by extending the functionality of available PFCs.
PFC is widely employed in household appliances as an active front-end AC/DC converter imposing unity power factor and supplying the load with the required constant DC voltage, while ensuring a high efficiency [22].PFC stages have traditionally been utilized to improve the electrical power quality of EPS by emulating an input resistance for all system frequencies, so that in the case of a sinusoidal grid voltage the input current is sinusoidal with very high-frequency harmonic distortion, linked to the switching ripple.However, this resistor emulator behavior will result in line current harmonics in the case of harmonically distorted grid voltages, which would contribute to maintain T HD V levels at the Point of Common Coupling (PCC).A digitally controlled boost PFC with variable input impedance is proposed in [23].The resistor emulator behavior is adjusted at different harmonic frequencies to contribute to the improvement of the grid stability.
Diverse works on PFC, impressing sinusoidal input currents (sinPFC), have previously been published.In [24], [25], a sine wave generator is employed within the current loop to generate the appropriate reference current in single-phase systems.The sine wave generator can be replaced by a Phase-Locked Loop (PLL), as in [26], to generate the reference signal.Predictive controllers with a current sensor, showing immunity to input voltage distortion are utilized in [27].These approaches are also employed in three-phase PFC in [28] and [29], respectively.The accurate synchronization of the modulation signals with the grid, the harmonics injected to compensate the distortion effect and the implementation of adaptive controllers to find the best response under distorted or non-distorted grid voltage motivate the utilization of digital controllers.The adoption of a sensorless solutions represents a step forward in terms of simplicity and reliability.As long as the resulting power factor is satisfactory, the elimination of the current sensor also eliminates the circuitry associated to the adoption of a reference for the current measurement, signal conditioning circuits and an analog-to-digital converter, in the case of a the controller implementation in a digital circuit.Since the current signal is not affected by the sensor size, the resulting controller covers a wider power rate.Several sensorless approaches have been presented recently.A voltage sensorless controller with adjustable power factor is proposed in [30] for a three-phase three-switch Vienna rectifier.A current sensorless technique with an artificial input voltage, stored in a Look-Up Table (LUT) to gain immunity under distorted input voltage, is presented in [31].A more sophisticated technique, which precalculates the duty-cycle sequence, extending the load range of application with no input voltage or current acquisition, assuming that the reference is sinusoidal is presented in [32].In [33], [34], a current sensorless technique is extended for multiphase current interleaved topologies.Since the actual current shape depends on the volt-seconds across the input inductor, the distortion of the AC input voltage produces input current distortion when the resistor emulator technique is used.
This paper proposes to improve the PF at the PCC by applying an adaptive PFC controller to the grid-connected AC/DC converters of a residential grid, introducing the concept of Power Quality Enhancer (PQE) (Fig. 1).This PQE adapts the AC/DC converter current depending on the grid distortion.In this way, the PFC controller can operate in both resistor emulator and sinusoidal input current modes, allowing the T HD V minimization in residential electrical grids while maintaining maximum PF at the PCC.The proposed PQE PFC helps to reach advanced specifications required in residential smartgrids, such as peak load reduction [35] and energy management [36].The paper is organized as follows.The main contributions are presented in Section II and III.Section II introduces the definitions of electrical power quantities and the effect of T HD I on the PF measured at the PCC and presents the PQE's operation principles.Details of the controller selected to develop the proof of concept [37] and the experimental results with the controller modified by the PQE are presented in Section III and IV respectively.

II. EFFECT OF THE PROPOSED CONTROLLER ON THE ELECTRICAL POWER QUALITY OF RESIDENTIAL GRIDS
The proposed PQE PFC consists of a conventional PFC stage with an enhanced digital controller, which adjusts the operation mode to maximize the P F while contributing to reduce the T HD V at the PCC.The proposed controller modification is shown in Fig. 1, where the local T HD V measurement is employed to adjust the PFC operation mode.For analysis purposes, as depicted in Fig. 1, the Low-Voltage (LV) residential grid and household appliances are modeled through their Thévenin and Norton equivalents respectively.In [38], an individual residential house is modeled by its equivalent impedance and a current source, representing the linear and non-linear loads respectively.Considering that most of the Conventional Household Appliances (CHA) are connected to the grid through unidirectional AC/DC converters, the house impedance is approximated by a pure resistor, R CHA , and a current source, corresponding to the sum of N − 1 current harmonics i CHA .Therefore, i CHA is given by (1), where N represents the maximum harmonic order, n, of the CHA current: Similarly, PQE PFC based household appliances are modeled through an equivalent resistor R eq and the harmonically distorted current i P QE , calculated with the difference between the PCC voltage (v P CC ) and its fundamental frequency component (v P CC,1 ), with M representing the maximum harmonic order of v P CC .The factor k is selected depending on the PCC T HD V .By applying k = 0, the PQE PFC behaves as a resistor emulator and with k = 1, a sinusoidal input current is achieved.Moreover, it must be considered that, behaving as a front-end converter and assuming a resistive load (R DC ) fed by the stationary voltage (V DC ) imposed by the PQE PFC outer voltage controller (Fig. 1), the input power of the PQE PFC (P in P QE ) is imposed by the PFC output power, with no dependence on the operation mode selected through k.The

Operation Mode Selector
Sensorless NLC Controller [35][36][37] Sinusoidal current mode [32] R PQE iPQE LV electrical grid, from the point of view of the household appliances, is modeled through the impedance Z g and v g : where v g,1 is the fundamental component of the grid voltage (v g ), v g,n its n th harmonic component, and L the maximum harmonic order of v g , with L ≤ M < N .Assuming the approach in IEEE Std.1459 [39], where the electrical power quantities under sinusoidal, non-sinusoidal, balanced and unbalanced conditions are defined, the instantaneous input power of the PQE PFC in Fig. 1 is written as Averaging p in P QE over a grid period T results in the active power of the PQE PFC (P in P QE ): V 2 P CC,n = where it has been assumed that the PCC voltage and R eq change slowly enough, η is the PQE PFC efficiency and P out P QE its output power, which, being employed as a front-end converter, means R DC (Fig. 1).Hence, the equivalent resistance of the PQE PFC is which, having P out P QE imposed by the PFC outer voltage control loop, depends on the PCC voltage and the selected operation mode (k).As a consequence, in the resistive emulator mode (k = 0) R eq increases with the T HD V .For simplicity's sake, it will be assumed that η = 100% in the subsequent analysis.

A. PF at the PCC with the PQE PFC controller in both operation modes
As will be proved in this subsection, the PF at the PCC can be improved by the PQE PFC in household appliances.The PF is evaluated through the definition in IEEE Std.1459 [39] and both operation modes (k = 1 and k = 0) are considered.From Fig. 1: and where P in CHA is the active power due to the CHA and the term P harm corresponds to the active power transferred by the harmonic current components due to the conventional load nonlinearities and the harmonic distortion of the PCC voltage.
The overall household appliance current (i g ) can be obtained from Kirchhoff's Current Law (KCL) at the PCC: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and, then, the squared rms value of the overall household appliance current is evaluated using (10): Substituting ( 10) into (7), the PF at the PCC is obtained: where S 2 0 and S 2 k are given in ( 12) and ( 13) respectively: Eq. ( 12) does not depend on k while S 2 k depends on the selected operation mode.Considering that k ∈ [0, 1] and P harm + P out P QE > 0, the value of k required to maximize the PF is obtained from (11) by minimizing the denominator, resulting in Identification of the optimal continuous value of k ∈ [0, 1] requires P harm to be known.In the following analysis only k = 0 or k = 1 values are allowed.Then, depending on the selected operating mode for the PQE PFC, the overall PF becomes where P out P QE only depends on the DC load of the PQE PFC, being independent on the selected k.Under the same grid and load conditions, a change in k results in a different PF at the PCC.The operation in a sinusoidal line current mode is the most beneficial if the following relationship is fulfilled  Therefore, the active power ratio P harm , which depends on the nonlinear household appliances, and the measured T HD V at the PCC are used to select the most appropriate k.It must be considered that in the case of P harm ≤ 0, (16) cannot be verified and the resistive emulator mode is the most beneficial.Condition ( 16) is depicted in Fig. 2, showing the operation mode that results in a better PF at the PCC depending on the T HD V and the P out P QE P harm ratio.By increasing the power processed through the proposed PQE PFCs, the overall PF will benefit from the resistor emulator mode (k = 0) or the sinusoidal current mode (k = 1) depending on the measured T HD V at the PCC.In the case of highly non-linear loads as CHA, the most beneficial operation mode in residential EPS (with relatively low T HD V ) is the sinusoidal current one (k = 1).If the power processed through the PQE PFCs is high enough, the resistor emulator mode (k = 0) would be the most beneficial one.As an illustrative example, given a certain P out P QE P harm , for instance 5000, the threshold value provided by eq. ( 17) is 2 %.Below this T HD V value, the PQE must operate in sinusoidal current mode to maximize the overall PF.
The overall system conditions allowing the operation in a sinusoidal line current mode are evaluated below.As has been established before, this operation mode requires where v pcc and i CHA are the phasor representation of the PCC voltage and the harmonic current due to the conventional loads in Fig. 1.By applying the superposition principle, and replacing Z g in Fig. 1 by R g + jL g , the condition (18), in terms of IEEE Std.1459 definitions and considering the PQE PFC operation mode through k, can be rewritten as where the term P A (k), given in (20), corresponds to the power term resulting from the interaction of conventional non-linear loads and the grid voltage harmonics while P B (k), the power term which is consequence of the voltage across the grid  impedances due to the harmonics caused by the non-linear loads, is directly computed by (21).From (19), having a grid voltage harmonically distorted above a given rate, the PFC operation in sinusoidal input current mode improves the PF.Otherwise, the resistor emulator mode results in better PF.Under the assumption of R CHA ≈ R eq , R g << R CHA , L g << R g and considering that I CHA,n decreases while increasing n, (19) can be approximated by where the contribution of the grid voltage harmonics to the active power must be greater than the effect of the harmonic currents through the grid impedance.
By substituting ( 22) into (17), under the previous assumptions, the following relationship must be accomplished in order to improve the overall PF by operating in sinusoidal input current mode Condition ( 23) is depicted in Fig. 3.The sinusoidal input current mode leads to a higher PF between the depicted surface and the T HD V = 0 % plane, i.e. underneath the surface.

B. PQE PFC concept simulations
The PQE PFC concept has been tested with simulations considering a typical feeder in a distribution grid.A scenario with 20 houses connected to the feeder, where the house and grid parameters have been obtained from [40]- [42], and CHA are a combination of Compact Fluorescent Lights (CFL) and Personal Computers (PC) adjusted to a nominal house power of 2.2 kW and a 230 V 50 Hz feeder voltage with harmonic distortion levels due to 5 th and 7 th harmonics, L g = 0.08 mH, R g = 60 mΩ.The simulations are carried out changing the number of conventional non-linear loads and PFCs ( P in P F C P P CC ), while maintaining the overall active power at the PCC (P P CC ), and measuring the overall P F at the PCC according to the scheme depicted in Fig. 1.The simulations have been carried out in MatLab/Simulink and show the applicability of the PQE PFC concept in residential EPS.
Fig. 4 shows the PF at the PCC due to the PQE PFC.The PQE controller selects the most beneficial operation mode (k = 1 or k = 0) following the approach in Section II.A.The alternative operation mode, discarded by the PQE, is also plotted for comparison purposes.As it is shown, the PCC PF increases by replacing conventional loads with PFCs but, at low grid T HD V (due to v g in Fig. 1), k = 1 performs better than k = 0 mode and the PQE controller assumes this operation mode to maximize the PF at the PCC.With PQE applying k = 1, and k = 0 discarded, the maximum difference between modes arises at pure sinusoidal grid voltage and P in P F C P P CC = 50%, where the PQE increases the P F from 0.988 to 0.989, meaning 120 VA.If all the power is processed through PQE PFCs and the grid T HD V reaches 8%, then k = 0 increases the PF with respect the k = 1 case, from P F = 0.995 up to virtually unity, reducing the reactive component by 4.17 kVA.The worst P F corresponds to only CHA loads, with P F = 0.955.

III. IMPLEMENTATION OF THE PQE CONTROLLER
According to the previous discussion, a sinusoidal line current contributes to increasing the efficiency and performance of the residential EPS within the conditions depicted in Fig. 2. The PQE can be included in any PFC controller.Without losing generality, this section describes the proposed singlephase sensorless controller for PFC achieving this behavior.The proposed approach extends the performance of the digital sensorless Non-Linear Controller (NLC) in PFC [37], [43]- [46] by including a new term, which depends on the measured voltage harmonic distortion and the DC load.This term achieves low T HD I current impression regardless of the line voltage distortion.The NLC has been selected to connect this proposal with recent research work [47].It shows a better dynamic performance compared to the linear controllers based on current averaging, especially for high-frequency grids.The main drawback is its poor noise immunity, overcome with the sensorless approach.A typical bandwidth of the linear current control loop recommended for utility line frequencies (50 − 60 Hz) is units of kHz, with switching frequencies close to 100 kHz.If the line frequency increases, the typical distortion around the line zero-crossing makes it impossible to fulfill the harmonic limits.This issue is addressed in detail in [48] and [49].Nonlinear controllers solve this problem, achieving responses as fast as the switching cycle [50].The NLC sensorless controller represents a solution suitable for universal voltage (85 to 250 V rms and grid frequencies up to 400 Hz), being attractive to prove the contribution of this paper.
The NLC is defined for the Boost converter switching at constant frequency, f sw = 1/T sw , and with Pulse-Width * corresponding author email: alberto.pigazo@unican.esModulation (PWM).A variable i av (t) is calculated during each switching period, 0 ≤ t ≤ T sw , from i reb (t), which is the output of the current rebuilding algorithm [51] shown in Fig. 5 and i 0 , which is the current at the beginning of the switching period.The carrier signal, v m , and i av are compared to set the duty cycle, d.
It is assumed that i av (dT sw ) represents the average current over the switching period when the estimation errors are properly compensated i.e. i av (dT sw ) = i P QE Tsw (25) To derive the sinPFC NLC for the PQE PFC, i P QE Tsw is firstly assumed sinusoidal, so that The controller with k = 0 results in an input current i P QE , i.e. i P QE Tsw , proportional to v P CC using the NLC technique as shown in Fig. 6 and summarized with the expression with the duty cycle d = t on /T sw and the carrier signal v m , whose amplitude, V m , is proportional to the input power, P in P QE , and also represents the inverse of the emulated resistance R eq . with where R s is a fictitious sensing resistance, which gives consistency to the units of the variables in the rebuilding algorithm.Considering a distorted AC line voltage at the PCC according to (3), ( 26) can be rewritten as a function of v P CC,1 where R provides proportionality between the input current i P QE and the fundamental component of the voltage v 1 .
Assuming that the converter operates in the Continuous Conduction Mode (CCM), the ideal quasi-static conversion characteristic of the PWM-controlled Boost converter with duty cycle d is given by and introducing ( 31) into (30) results in Around the AC line zero crossing, where the converter operates in the Discontinuous Conduction Mode (DCM), a little distortion in the input current occurs as is explained in detail in [34] for the traditional NLC controller, affecting this low T HD I controller in the same way.In CCM, the NLC control achieves power factor correction through a comparison of signals (Fig. 6) that finds an easy implementation in a digital circuit.
The output voltage is approximated in (31) and ( 32) by its DC value (small ripple approximation) at the specified reference level V DC = V ref DC .The first term in (32), V DC (1−d)/R, is similar to the NLC control law shown in [34] or the Linear Peak Current-Mode (LPCM) control in [52].The second term, v P CC,H /R, corresponds to line harmonic voltage distortion and factor k allows the T HD V to be considered.The duty cycle command is obtained by comparing the digitized signals i av (t) and a leading-edge saw-tooth carrier signal v m (t), redefined as where For the current sensorless application, R s = 1 Ω is arbitrarily adopted, where the value R changes with the load and is set by the outer voltage loop with V m [43].The second term in (33), kR s v P CC,H /R, offsets the carrier signal in each switching period, meaning a lowfrequency harmonic content in the carrier signal.With the factor k defined in the previous section, the operation mode of the PFC is selected.Fig. 7 shows the waveforms defined in (33) and the lowest harmonics over a half line cycle, for an input voltage with a T HD V = 6 % with harmonics v P CC,3 = 0.05 √ 2 sin(3ωt), v P CC,5 = 0.03 √ 2 sin(5ωt + π) and v P CC,7 = 0.01 √ 2 sin(7ωt).For clarification purposes, T sw has been depicted much longer than the actual implemented switching period.In order to obtain the second term in (33), an Analog-to-Digital Converter (ADC) digitizes the input voltage, v P CC , and a sinusoidal pattern is synchronized with the utility line-toneutral voltage using a digital Zero-Crossing Detector (ZCD).An input voltage peak detector is used to approximate the value of v P CC,1 to v P CC,1 ≈ V P CC,peak sin(ωt).Different approaches, such as the zero-phase detector circuit in [53] or PLLs can be applied here, the last one being the preferred approach to achieve immunity to input voltage distortion [54], [55], as is included in certain PFC proposals [56], [57].Hence, (30) is rewritten as where ω is evaluated on a period-to-period basis and, assuming slow harmonic variations, their effect on ω are negligible.Estimation errors occur due to the phase displacement of sin(ωt) and the fundamental in v P CC , which are caused by the relative phase and magnitude of the voltage harmonics in v P CC .Replacing the ZCD by a PLL avoids such effects, however, it must be considered that the T HD V in residential feeders is usually in the range (1%,3%) [58], which limits the potential phase errors to less than a maximum 3.3 degrees.The effects of the voltage harmonic distortion on the estimation of V P CC,peak are mitigated by the outer voltage control loop of the PQE, which adjusts the amplitude of i P QE .If i P QE , which is purely sinusoidal according to (30), is initially different to the one required by the load, then the outer voltage loop modifies V m , and therefore R, to set the input current according to the required power.
A block diagram of the Boost rectifier with the low T HD I controller and its connection to the operation mode selector is shown in Fig. 1 The calculation of the voltage distortion can be improved using a specific algorithm implemented in a digital device, i.e. a microcontroller or an Field Programmable Gate Array (FPGA), the Fast Fourier Transforms (FFT) is a good choice to obtain the harmonic content of a variable, with dedicated blocks to compute this, like in [59], [60], but this requires lots of resources.On the other hand, the outer loop makes an accurate calculation of the distortion term unnecessary and the value of each harmonic voltage is not needed, so the total harmonic voltage v P CC,H is computed, with the outer voltage loop setting the value of V m .In steady-state, R automatically defines the amplitude < i P QE > Tsw [46].Note that with the PQE controller, the load viewed by the grid, R eq , is now a function of the input voltage phase.In steady state, and for a defined input power P in P QE , the input current in (26), and (34) yields an expression for R R = V P CC,peak V P CC,1 From (35), it is possible to obtain the expression for the equivalent resistance R eq IV. EXPERIMENTAL RESULTS With the addition of the proposed modification to the NLC controller, the parameter k selects the preferred behavior   depending on the application, either resistor emulator or low T HD I .
To experimentally validate this proposal, the Boost converter has been tested under two input voltages (120 V rms and 230 V rms ) and three input frequencies (50 Hz, 60 Hz and 400 Hz), with 12 % harmonic distortion, for two different power levels (around 330 W and 800 W ), and 96 kHz switching frequency.These situations have been tested with the PQE controller in both pure sinusoidal and resistor emulator behavior modes, and the results are summarized in Table I.A Pacific 345-AMX AC power source is used to supply the front-end stage with a distorted voltage.Different templates of distorted voltages are predefined.The T HD I results, which include all the harmonics required by the standards, are also provided by the AC power source.Comparing the results presented in Table I, it can be observed that the highest power factor values are obtained, as expected, with the resistor emulator behavior, with a T HD I similar to the T HD V of the input voltage; obtaining a power factor similar to the obtained with pure sinusoidal grid voltage.On the other hand, with the new proposal, the current harmonics are lower (above all 3 rd and 5 th harmonics) than the voltage ones and therefore the T HD I is also lower than the T HD V .Fig. 8.a and 8.b show the voltage and current waveforms of the PQE PFC in resistor emulator and sinusoidal current modes respectively at 50 Hz.In resistor emulator mode the current waveform is proportional to the voltage one and, hence, current harmonics (the blue bars in Fig. 8.c) will generate voltage harmonics at the PCC due to Z g in Fig. 1.By changing the operation mode to sinusoidal current one, the T HD I reduces from 11.5 % to 4.2 % and the current waveform in Fig. 8.b is almost sinusoidal but the zero crossing.Since the EPQ PFC active power is almost constant (≈ 820 W ) in both operation modes, the fundamental input current must increase to compensate for the active power transferred by the current harmonics in the resistor emulator mode.
The proposed PQE PFC performance has also been evaluated in 60 Hz EPS, as it is shown in Fig. 9.a and 9.b.The results are similar to the 50 Hz case.Input current ripple is higher because the DC output voltage is intentionally lower in these tests to verify that the PQE controller performance does not depend on the output voltage level.As it is shown in Fig. 9.c, the input current spectra in both operation modes follow the behavior observed in the 50 Hz case.
Finally, in order to show the applicability of this approach to airplane EPS, the PQE PFC has been connected to a 400 Hz grid voltage and the obtained results are shown in Fig. 10.Again, the performance of the PQE PFC is consistent with the previous cases (Fig. 10.c).The results of all the cases are summarized in Table I.
The lower distortion observed as the line frequency increases is a consequence of the applied technique without current sensor [46].This technique compensates for the current estimation errors acquired around the zero line crossing and therefore the accumulated error during half the line period becomes lower as the line frequency increases.

V. CONCLUSION
The consequence on the electrical power quality of connecting household appliances to the grid through PFC stages has been assessed considering different T HD V scenarios.As has been shown in (17) and (23), there are conditions under which sinusoidal current consumption results in better PF at the PCC than with resistor emulator behavior, commonly assumed to be ideal for PFC stages.A modification of the carrier signal of NLC controllers applied to PFC stages is designed to impress sinusoidal input current despite the input voltage distortion.The line current estimation with no interaction with the power stage implements the NLC with high noise immunity.The digital implementation of the non-linear controller is appropriate to define the carrier and to include additional reduction of the current distortion depending on the application.The PQE controller can be applied to mitigate the effect of nonlinear loads within household appliances on residential electrical grids.The operation mode of the digital controller can be autonomously adjusted through the locally measured T HD V , without extra circuitry.The user or a T HD V threshold detection selects the convenient behavior (either resistor emulator or pure sinusoidal current).Experimental results obtained with high T HD V (above 5 %) confirm the feasibility of the PQE controller in both sinusoidal current and resistive emulator modes.

Fig. 1 .
Fig. 1.Residential LV grid with household appliances feed through conventional AC/DC stages (without the proposed operation mode selector) and the proposed PQE controller.

Fig. 2 .
Fig. 2. Operation region of the PQE PFC resulting in a higher PF (P harm > 0).

Fig. 4 .
Fig. 4. PF at the PCC due to the PQE and the discarded operation modes.a) P in P F C P P CC = 25% b) P in P F C P P CC = 60% c) P in P F C P P CC = 90%.

Fig. 7 .
Fig. 7. Carrier and v P CC,H in an example of input voltage with T HD V = 6%.
. The proposed circuit obtains a signal that represents the input voltage distortion with |v P CC,H | ≈ |v P CC | − v P CC,peak |sin(ωt)|.

Fig. 8 .
Fig. 8. Experimental results of PQE PFC at 50 Hz.Voltage and current waveforms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

Fig. 9 .
Fig. 9. Experimental results of PQE PFC at 60 Hz.Voltage and current waveforms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

Fig. 10 .
Fig. 10.Experimental results of PQE PFC at 400 Hz.Voltage and current waveforms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

TABLE I EXPERIMENTAL
RESULTS UNDER DISTORTED LINE VOLTAGE