Reducción de la frecuencia de muestreo en los conversores ADC y DAC usados en predistorsionadores digitales

Abstract

With the increasing demands for higher data rate, wider signal bandwidth is required, and this imposes high sampling rate converters in the communications equipment. This paper provides and analyzes experimental results obtained from testing some of the most promising techniques able to reduce the sampling rate speed of the analog to digital converters and digital to analog converters to be used in the implementation of Digital Predistorters. In a first section, an overview of several of the recently published sampling rate reduction techniques is done, and later it’s included a section where the author’s activities related to the digital predistortion of wideband signals are explained, and some of their last research activities and results in sampling rate and bandwidth reduction are provided.