New scalable cache coherence protocols for on-chip multiprocessors

Abstract

RESUMEN: En esta tesis se lleva a cabo un análisis sobre la problemática asociada a la coherencia cache en el ámbito de los Multiprocesadores en chip (CMPs) y se presentan dos nuevas propuestas de protocolos de coherencia basada en hardware. Ambas propuestas van dirigidas a mitigar el coste asociado a la imperiosa necesidad de emplear jerarquías de memoria complejas dentro del chip que buscan superar la limitación del ancho de banda a memoria (bandwidth-wall). Así, por un lado, considerando como objetivo los sistemas multicore, compuestos por unas decenas de procesadores dentro del chip, se propone LOCKE, un protocolo de coherencia basado en broadcast y centrado en mejorar la reactividad de la jerarquía de memoria on-chip. Por otro lado, para futuros sistemas CMPs de gran escala que incluirán cientos o miles de procesadores, se propone MOSAIC, un protocolo escalable hibrido broadcast-directorio que logra disminuir significativamente el coste del mantenimiento de la coherencia hardware.

ABSTRACT: This thesis includes an analysis of the problems associated with cache coherence in the field of chip multiprocessors (CMPs) and it introduces two new hardware-based coherence protocol proposals. Both proposals are focused on mitigating the associated cost brought by the necessity of having to use complex memory hierarchies inside the chip in order to face the memory bandwidth limitation (bandwidth-wall). On the one hand, considering as a target multicore systems with tens of processors within the chip, LOCKE is proposed. This proposal uses a broadcast-based approach, which focuses on improving the reactiveness of the on-chip memory hierarchy. On the other hand, for future large-scale CMPs which will include hundreds or thousands of processors, MOSAIC is proposed. This is a scalable hybrid coherence protocol (broadcast- and directory-based) that significantly reduces the maintenance costs of hardware coherence.