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dc.contributor.authorLamo Anuarbe, Paula
dc.contributor.authorLópez Vidal, Felipe 
dc.contributor.authorPigazo López, Alberto 
dc.contributor.authorAzcondo Sánchez, Francisco Javier 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2025-11-28T14:52:13Z
dc.date.available2025-11-28T14:52:13Z
dc.date.issued2018-06
dc.identifier.issn2168-6777
dc.identifier.issn2168-6785
dc.identifier.otherTEC2014-52316-Res_ES
dc.identifier.urihttps://hdl.handle.net/10902/38312
dc.description.abstractBridgeless power factor correction (PFC) stages and the associated current shaping techniques require grid synchronization to ensure unity displacement power factor. In controllers with no current sensor, line current rebuilding algorithms are especially sensitive to synchronization issues. Phase-locked loops (PLLs) are used to synchronize the control of grid-connected converters, and may include a secondary control path to improve their dynamics in the case of grid disturbances. This paper presents linear models of T/4 PLLs with secondary control paths. The T /4 PLL structures are digitized and their performance evaluated. The stability conditions are determined. The PLL signal is utilized for current sensorless bridgeless PFCs, in the current estimation algorithm to reduce the estimation error, and as the reference in the current controller. The effect of the response of different PLLs on the PFC under grid disturbances is evaluated experimentally.es_ES
dc.description.sponsorshipThis work was supported by the Spanish Ministry of Economy and Competitiveness under Grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices.es_ES
dc.format.extent12 p.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.sourceIEEE Journal of Emerging and Selected Topics in Power Electronics, 2018, 6(2), 674-685es_ES
dc.subject.otherBridgelesses_ES
dc.subject.otherConverteres_ES
dc.subject.otherFeedbackes_ES
dc.subject.otherPhase-locked loop (PLL)es_ES
dc.subject.otherSecondary control pathes_ES
dc.subject.otherSensorlesses_ES
dc.subject.otherStabilityes_ES
dc.subject.otherSynchronizationes_ES
dc.subject.otherT/4es_ES
dc.titleStability and performance assessment of single-phase T/4 PLLs with secondary control path in current sensorless bridgeless PFCses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/JESTPE.2018.2791360es_ES
dc.rights.accessRightsopenAccesses_ES
dc.identifier.DOI10.1109/JESTPE.2018.2791360
dc.type.versionacceptedVersiones_ES


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