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dc.contributor.authorDávila Guzmán, María Angélica
dc.contributor.authorNozal, Raúl 
dc.contributor.authorGran Tejero, Rubén
dc.contributor.authorVillarroya-Guadó, María
dc.contributor.authorSuárez Gracia, Darío
dc.contributor.authorBosque Orero, José Luis 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2025-01-20T14:21:35Z
dc.date.available2025-01-20T14:21:35Z
dc.date.issued2019-03
dc.identifier.issn0920-8542
dc.identifier.issn1573-0484
dc.identifier.otherTIN2016-76635-C2es_ES
dc.identifier.urihttps://hdl.handle.net/10902/35074
dc.description.abstractHeterogeneous systems are the core architecture of most of the high-performance computing nodes, due to their excellent performance and energy efficiency. However, a key challenge that remains is programmability, specifically, releasing the programmer from the burden of managing data and devices with different architectures. To this end, we extend EngineCL to support FPGA devices. Based on OpenCL, EngineCL is a high-level framework providing load balancing among devices. Our proposal fully integrates FPGAs into the framework, enabling effective cooperation between CPU, GPU, and FPGA. With command overlapping and judicious data management, our work improves performance by up to 96% compared with single-device execution and delivers energy-delay gains of up to 37%. In addition, adopting FPGAs does not require programmers to make big changes in their applications because the extensions do not modify the user-facing interface of EngineCL.es_ES
dc.description.sponsorshipThis work was supported in part by grants TIN2016-76635-C2 (AEI/FEDER, UE), gaZ: T48 research group (Aragón Gov. and European ESF), the University of Zaragoza (JIUZ-2017-TEC-09), HiPEAC4 (European H2020/687698), the Spanish Ministry of Education (FPU16/03299) and the CAPAP-H Network grant TIN2016-81840-REDT. M. A. Dávila-Guzmán is supported by a Universidad de Zaragoza-Banco Santander PhD scholarship.es_ES
dc.format.extent15 p.es_ES
dc.language.isoenges_ES
dc.publisherKluwer Academic Publisherses_ES
dc.rights© Springer Science+Business Media, LLC, part of Springer Nature 2019. This version of the article has been accepted for publication, after peer review (when applicable) and is subject to Springer Nature's AM terms of use, but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: http://dx.doi.org/10.1007/s11227-019-02768-yes_ES
dc.sourceJournal of Supercomputing, 2019, 75(3), 1732-1746es_ES
dc.subject.otherHeterogeneous schedulinges_ES
dc.subject.otherFPGAes_ES
dc.subject.otherLoad Balancinges_ES
dc.subject.otherOpenCLes_ES
dc.titleCooperative CPU, GPU, and FPGA heterogeneous execution with EngineCLes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherVersionhttps://doi.org/10.1007/s11227-019-02768-yes_ES
dc.rights.accessRightsopenAccesses_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI//TIN2016-76635-C2-2-R/ES/REDES DE INTERCONEXION Y SISTEMAS HETEROGENEOS/es_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI//TIN2016-76635-C2-2-R/ES/REDES DE INTERCONEXION Y SISTEMAS HETEROGENEOS/es_ES
dc.identifier.DOI10.1007/s11227-019-02768-y
dc.type.versionacceptedVersiones_ES


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