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dc.contributor.authorGómez Varela, Raúl 
dc.contributor.authorAledo Ortega, David 
dc.contributor.authorPosadas Cobo, Héctor 
dc.contributor.authorVillar Bonet, Eugenio, 1957- 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2024-12-10T19:10:27Z
dc.date.available2024-12-10T19:10:27Z
dc.date.issued2024
dc.identifier.isbn979-8-3503-6439-2
dc.identifier.otherPID2020-116417RB-C43es_ES
dc.identifier.urihttps://hdl.handle.net/10902/34596
dc.description.abstractIn Embedded and Cyber-Physical Systems (E&CPS) the functional and temporal interactions between the digital and physical parts are crucial. In these systems, most of the functionality is implemented by software deployed on heterogeneous, distributed platforms so its performance largely affects the whole E&CPS behavior. Their HW/SW co-design requires fast and accurate simulation tools capable of evaluating the performance of each platform configuration for the applications selected while minimizing software porting needs. Host-compiled simulation avoids porting, but has limitations to obtain accurate results due to the difficulty of extracting and modeling the microarchitectural details of the target platforms while maintaining simulation speed. To solve that, this work proposes replacing the traditional approach of generating code annotations with all processor internal details by the use of neural networks. Training the neural network for a specific processor enables considering its internal details when estimating the cost of executing each basic block of the software in the target processor.es_ES
dc.description.sponsorshipThe authors would like to thank TEKNE for letting us to use their use case to validate our tool. This work has been partially funded by the EU and the Spanish Mineco through the ECSEL Joint Undertaking (JU) under grant agreement N. 101007350 and the PID2020-116417RB-C43, TALENT project.es_ES
dc.format.extent6 p.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineers, Inc.es_ES
dc.rights© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.sourceXXXIX Conference on Design of Circuits and Integrated Systems (DCIS), Catania, Italy, 2024, 165-170es_ES
dc.titleAI-based estimation of embedded software execution cycles in host-compiled simulationes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/DCIS62603.2024.10769196es_ES
dc.rights.accessRightsopenAccesses_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/H2020/101007350/EU/AI-augmented automation for efficient DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems/AIDOaRt/es_ES
dc.identifier.DOI10.1109/DCIS62603.2024.10769196
dc.type.versionacceptedVersiones_ES


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