dc.contributor.author | Gómez Varela, Raúl | |
dc.contributor.author | Aledo Ortega, David | |
dc.contributor.author | Posadas Cobo, Héctor | |
dc.contributor.author | Villar Bonet, Eugenio, 1957- | |
dc.contributor.other | Universidad de Cantabria | es_ES |
dc.date.accessioned | 2024-12-10T19:10:27Z | |
dc.date.available | 2024-12-10T19:10:27Z | |
dc.date.issued | 2024 | |
dc.identifier.isbn | 979-8-3503-6439-2 | |
dc.identifier.other | PID2020-116417RB-C43 | es_ES |
dc.identifier.uri | https://hdl.handle.net/10902/34596 | |
dc.description.abstract | In Embedded and Cyber-Physical Systems (E&CPS) the functional and temporal interactions between the digital and physical parts are crucial. In these systems, most of the functionality is implemented by software deployed on heterogeneous, distributed platforms so its performance largely affects the whole E&CPS behavior. Their HW/SW co-design requires fast and accurate simulation tools capable of evaluating the performance of each platform configuration for the applications selected while minimizing software porting needs. Host-compiled simulation avoids porting, but has limitations to obtain accurate results due to the difficulty of extracting and modeling the microarchitectural details of the target platforms while maintaining simulation speed. To solve that, this work proposes replacing the traditional approach of generating code annotations with all processor internal details by the use of neural networks. Training the neural network for a specific processor enables considering its internal details when estimating the cost of executing each basic block of the software in the target processor. | es_ES |
dc.description.sponsorship | The authors would like to thank TEKNE for letting us to use their use case to validate our tool. This work has been partially funded by the EU and the Spanish Mineco through the ECSEL Joint Undertaking (JU) under grant agreement N. 101007350 and the PID2020-116417RB-C43, TALENT project. | es_ES |
dc.format.extent | 6 p. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers, Inc. | es_ES |
dc.rights | © 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
dc.source | XXXIX Conference on Design of Circuits and Integrated Systems (DCIS), Catania, Italy, 2024, 165-170 | es_ES |
dc.title | AI-based estimation of embedded software execution cycles in host-compiled simulation | es_ES |
dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
dc.relation.publisherVersion | https://doi.org/10.1109/DCIS62603.2024.10769196 | es_ES |
dc.rights.accessRights | openAccess | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/H2020/101007350/EU/AI-augmented automation for efficient DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems/AIDOaRt/ | es_ES |
dc.identifier.DOI | 10.1109/DCIS62603.2024.10769196 | |
dc.type.version | acceptedVersion | es_ES |