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dc.contributor.authorGómez Fernández, María del Carmen
dc.contributor.authorGarcía García, José Ángel 
dc.contributor.authorPedro, Jose Carlos Esteves Duarte
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2013-09-24T06:25:48Z
dc.date.available2013-09-24T06:25:48Z
dc.date.issued2004-09
dc.identifier.urihttp://hdl.handle.net/10902/3400
dc.description.abstractIn this paper, the use of a gate bias resistor is proposed for conforming a wide linearity sweet-spot in class B or C amplifiers based on junction FET technologies. An illustrative E-pHEMT transistor has been characterized in terms of its intermodulation distortion (IMD) behaviour versus input power, paying particular attention to the evolution of the gate-to-source voltage where the sweet-spot appears. The DC current, resulting from rectification of large gate-to-source voltage swings, has also been studied. It proved to be useful as an element for dynamically adjusting VGS with the RF power level, through the addition of an adequate resistor in the DC path. Finally, experimental results of this sweet-spot enhancement in both B and C amplifying classes are shown, either using the classical two-tone excitation or a real IS-95 modulated signal.es_ES
dc.format.extent4 p.es_ES
dc.language.isospaes_ES
dc.rights© 2004 URSI Españaes_ES
dc.sourceURSI 2004, XIX Simposium Nacional de la Unión Científica Internacional de Radio, Barcelonaes_ES
dc.titleControl del sweet-spot de IMD en dispositivos FET usando una resistencia de polarización de puertaes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.accessRightsopenAccesses_ES
dc.type.versionpublishedVersiones_ES


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