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dc.contributor.authorGarcía Villaescusa, David 
dc.contributor.authorAldea Rivas, Mario 
dc.contributor.authorGonzález Harbour, Michael 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2024-05-23T18:31:30Z
dc.date.available2024-05-23T18:31:30Z
dc.date.issued2023
dc.identifier.issn1383-7621
dc.identifier.otherTIN2017-86520-C3-3-R (PRECON-I4)es_ES
dc.identifier.urihttps://hdl.handle.net/10902/32916
dc.description.abstractScheduling models can be used to evaluate whether a particular system is able to meet its timing constrains. In many-core processors, with tens to hundreds of processors in the same chip, the analysis of the timing behavior needs to include the communications network used to exchange messages between the different processors. This paper presents a schedulability model for many-core systems based on a 2D mesh network-on-chip and store-and-forward switching with a limitation on the maximum link utilization rate that makes the analysis tractable. The model has been applied to the Epiphany many-core processor which has 16 cores connected by a 4 × 4 2D mesh. The analysis results have been tested on the real hardware by executing examples with synthetic task workloads. Those tasks are executed in a micro-kernel RTOS that we have developed. We also describe synchronization mechanisms to send messages between the tasks, and we analyze their timing behavior, so that they can be included in the analysis model.es_ES
dc.description.sponsorshipThis work was supported in part by the Graduate Grant Program of the Universidad de Cantabria and by the Spanish Government and FEDER funds (MCIN/AEI/10.13039/501100011033/FEDER) "Una manera de hace Europa" under Grant TIN2017-86520-C3-3-R(PRECON-I4).es_ES
dc.format.extent20 p.es_ES
dc.language.isoenges_ES
dc.publisherElsevieres_ES
dc.rights© 2023 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/)es_ES
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.sourceJournal of Systems Architecture, 2023, 134, 102762es_ES
dc.subject.otherReal-timees_ES
dc.subject.otherSchedulinges_ES
dc.subject.otherModelinges_ES
dc.subject.otherNetwork-on-chipes_ES
dc.subject.otherMany-corees_ES
dc.subject.otherMASTes_ES
dc.subject.otherParallellaes_ES
dc.subject.otherEpiphanyes_ES
dc.titleResponse-time analysis of mesh-based many-core systemses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1016/j.sysarc.2022.102762es_ES
dc.rights.accessRightsopenAccesses_ES
dc.identifier.DOI10.1016/j.sysarc.2022.102762
dc.type.versionpublishedVersiones_ES


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Mostrar el registro sencillo

© 2023 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/)Excepto si se señala otra cosa, la licencia del ítem se describe como © 2023 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/)