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dc.contributor.authorCamarero Coterillo, Cristobal 
dc.contributor.authorMartínez Fernández, María del Carmen 
dc.contributor.authorBeivide Palacio, Ramón 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2024-02-05T14:16:59Z
dc.date.available2024-02-05T14:16:59Z
dc.date.issued2015-09
dc.identifier.issn1045-9219
dc.identifier.issn1558-2183
dc.identifier.otherTIN2010-21291-C02-02es_ES
dc.identifier.otherTIN2013-46957-C2-2-Pes_ES
dc.identifier.urihttps://hdl.handle.net/10902/31430
dc.description.abstractTorus networks of moderate degree have been widely used in the supercomputer industry. Tori are superb when used for executing applications that require near-neighbor communications. Nevertheless, they are not so good when dealing with global communications. Hence, typical 3D implementations have evolved to 5D networks, among other reasons, to reduce network distances. Most of these big systems are mixed-radix tori, which are not the best option for minimizing distances and efficiently using network resources. This paper is focused on improving the topological properties of this kind of networks. By using integral matrices to deal with Cayley graphs over Abelian groups, we have been able to propose and analyze a family of high-dimensional mesh-based interconnection networks. As they are built over n-dimensional grids that induce a regular tiling of space, these topologies have been denoted lattice graphs. Higher dimensional networks can be composed over these graphs by means of a lift operation, which is also introduced in the paper. Easy network partitioning and minimal routing algorithm are also provided for these topologies based on this new network operation. Later we focus on cubic crystal lattices for modeling symmetric 3D networks and to show how lattice graphs can help in the design of twisted interconnection networks. In all cases, the networks obtained are better, in topological terms, than their standard tori counterparts. Finally, some practical issues such as implementability and preliminary performance evaluations have been addressed at the end of this work.es_ES
dc.description.sponsorshipThis work has been supported by the Spanish FPU grant AP2010-4900, the Spanish Science and Technology Commission (CICYT) under contracts TIN2010-21291-C02-02 and TIN2013-46957-C2-2-P, the European Union FP7 under Agreements ICT-288777 (Mont-Blanc) and ERC-321253 (RoMoL), the European HiPEAC Network of Excellence and the JSA no. 2013-119 as part of the IBM/BSC Technology Center for Supercomputing agreement.es_ES
dc.format.extent22 p.es_ES
dc.language.isoenges_ES
dc.publisherIEEE Computer Societyes_ES
dc.rights© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.sourceIEEE Transactions on Parallel and Distributed Systems, 2015, 26(9), 2506 - 2519es_ES
dc.titleLattice Graphs for High-Scale Interconnection Topologieses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/TPDS.2014.2355827es_ES
dc.rights.accessRightsopenAccesses_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/FP7/288777/EU/MONT-BLANC, European scalable and power efficient fpc platform based on low-power embedded technology/MONT-BLANC/es_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL/
dc.identifier.DOI10.1109/TPDS.2014.2355827
dc.type.versionacceptedVersiones_ES


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