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dc.contributor.authorSchares, Laurent
dc.contributor.authorLee, Benjamin G.
dc.contributor.authorChecconi, Fabio
dc.contributor.authorBudd, Russell
dc.contributor.authorRylyakov, Alexander
dc.contributor.authorDupuis, Nicolas
dc.contributor.authorPetrini, Fabrizio
dc.contributor.authorSchow, Clint L.
dc.contributor.authorFuentes Saez, Pablo 
dc.contributor.authorMattes, Oliver
dc.contributor.authorMinkenberg, Cyriel
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2024-01-30T16:02:37Z
dc.date.available2024-01-30T16:02:37Z
dc.date.issued2014-09
dc.identifier.issn0272-1732
dc.identifier.issn1937-4143
dc.identifier.urihttps://hdl.handle.net/10902/31327
dc.description.abstractData-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.es_ES
dc.description.sponsorshipThis work was supported by DARPA/ARL under contract W911NF-11-2-0059.es_ES
dc.format.extent12 p.es_ES
dc.language.isoenges_ES
dc.publisherIEEE Computer Societyes_ES
dc.rightsAlojado según Resolución CNEAI 5/12/23 (ANECA) © 2014 IEEEes_ES
dc.sourceIEEE Micro, 2014, 34(5), 52 - 63, 77es_ES
dc.subject.otherBandwidthes_ES
dc.subject.otherComputer architecturees_ES
dc.subject.otherData centerses_ES
dc.subject.otherDistributed computinges_ES
dc.subject.otherGraph exploration algorithmes_ES
dc.subject.otherHigh performance computinges_ES
dc.subject.otherHigh-speed optical techniqueses_ES
dc.subject.otherNetworkinges_ES
dc.subject.otherOptical fiber networkses_ES
dc.subject.otherOptical networkes_ES
dc.subject.otherOptical switcheses_ES
dc.subject.otherOptical switchinges_ES
dc.titleA throughput-optimized optical network for data-intensive computinges_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.accessRightsclosedAccesses_ES
dc.identifier.DOI10.1109/MM.2014.77
dc.type.versionpublishedVersiones_ES


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