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    A throughput-optimized optical network for data-intensive computing

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    Identificadores
    URI: https://hdl.handle.net/10902/31327
    DOI: 10.1109/MM.2014.77
    ISSN: 0272-1732
    ISSN: 1937-4143
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    Autoría
    Schares, Laurent; Lee, Benjamin G.; Checconi, Fabio; Budd, Russell; Rylyakov, Alexander; Dupuis, Nicolas; Petrini, Fabrizio; Schow, Clint L.; Fuentes Saez, PabloAutoridad Unican; Mattes, Oliver; Minkenberg, Cyriel
    Fecha
    2014-09
    Derechos
    Alojado según Resolución CNEAI 5/12/23 (ANECA) © 2014 IEEE
    Publicado en
    IEEE Micro, 2014, 34(5), 52 - 63, 77
    Editorial
    IEEE Computer Society
    Palabras clave
    Bandwidth
    Computer architecture
    Data centers
    Distributed computing
    Graph exploration algorithm
    High performance computing
    High-speed optical techniques
    Networking
    Optical fiber networks
    Optical network
    Optical switches
    Optical switching
    Resumen/Abstract
    Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.
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    UNIVERSIDAD DE CANTABRIA

    Repositorio realizado por la Biblioteca Universitaria utilizando DSpace software
    Contacto | Sugerencias
    Metadatos sujetos a:licencia de Creative Commons Reconocimiento 4.0 España