| dc.contributor.author | Pigazo López, Alberto | |
| dc.contributor.author | Azcondo Sánchez, Francisco Javier | |
| dc.contributor.author | Brañas Reyes, Christian | |
| dc.contributor.author | Lamo Anuarbe, Paula | |
| dc.contributor.author | Casanueva Arpide, Rosario | |
| dc.contributor.author | Díaz Rodríguez, Francisco Javier | |
| dc.contributor.other | Universidad de Cantabria | es_ES |
| dc.date.accessioned | 2024-01-25T15:31:09Z | |
| dc.date.available | 2024-01-25T15:31:09Z | |
| dc.date.issued | 2023 | |
| dc.identifier.isbn | 979-8-3503-1618-6 | |
| dc.identifier.other | PID2021-128941-OB-100 | es_ES |
| dc.identifier.uri | https://hdl.handle.net/10902/31267 | |
| dc.description.abstract | Bridgeless Power Factor Correctors (PFC) with a controller utilizing rectified ac variables can benefit from well-established strategies and circuits employed in PFCs with diode-bridge front-end. The grid voltage polarity is detected to compute the rms value of the grid voltage, and also used to generate and route the gate signals for the power devices. However, depending on the implementation, grid voltage disturbances may propagate through the polarity detection and RMS calculation stages, leading to a degradation of the input current and output voltage. This issue is addressed in this manuscript by investigating a single-phase bridgeless totem-pole (TP) PFC through simulation and proposing the replacement of the conventional implementation with a frequency-locked loop (FLL) to enhance the converter dynamics. | es_ES |
| dc.description.sponsorship | This work has been partially supported by the Spanish Ministry of Science and Innovation under grant PID2021-128941-OB-100: “Efficient Energy Transformation in Industrial Environments” (TRENTI). | es_ES |
| dc.format.extent | 6 p. | es_ES |
| dc.language.iso | eng | es_ES |
| dc.publisher | Institute of Electrical and Electronics Engineers, Inc. | es_ES |
| dc.rights | © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
| dc.source | IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, Michigan, 2023, 504-509 | es_ES |
| dc.subject.other | Power factor corrector (PFC) | es_ES |
| dc.subject.other | Bridgeless totempole (TP) | es_ES |
| dc.subject.other | Zero-crossing detector (ZCD) | es_ES |
| dc.subject.other | Frequency-locked loop (FLL) | es_ES |
| dc.title | Improving the dynamic performance of bridgeless PFC controllers with zero crossing detector and root-mean-square calculation blocks | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.rights.accessRights | openAccess | es_ES |
| dc.identifier.DOI | 10.1109/COMPEL52896.2023.10220445 | |
| dc.type.version | acceptedVersion | es_ES |
