Caracterización de niveles trampa en transistores HEMT de GaN

Abstract

This work presents the description of trapping effects in GaN HEMT’s. Two different effects will be considered: gate-lag and drain-lag, describing their physical origin. Virgin and aged devices will be used as test vehicles to study the dependence on the manufacturing process of the devices electrical behaviour. From a macroscopic point of view, both phenomena are quite different, so whilst gate-lag depends on Vgs voltage, drain-lag depends on the Vds one. Considering differences between virgin and aged devices, a conclusion about the dependence of trap levels on both thermal and electrical stress could be extracted.