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dc.contributor.advisorRorsman, Niklas
dc.contributor.authorTelechea González, Héctor 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2022-07-26T10:08:07Z
dc.date.issued2022-07-22
dc.identifier.urihttp://hdl.handle.net/10902/25391
dc.description.abstractABSTRACT: This project concerns the design and optimization of GaN HEMT. This optimization is going to be achieved by extracting the different parasitic elements that appear on a transistor. In this way, it is possible to reduce its effect and discover what are the advantages and disadvantages introduced for this type of parasitic elements. These parasitic elements are divided into two separate categories: intrinsic and extrinsic parasitic elements. It is going to be considered different modifications to the layout of the transistor, such as changing physical dimensions or removing /adding different parts. Therefore, it is going to observe the main differences between dissimilar layouts and layouts with/without one specific part. Another objective is to set a small signal equivalent circuit. This equivalent circuit can model the behavior of this type of transistor to know most of the lumped elements that are included on a GaN HEMT at low and high frequencies. That’s why is desirable to design a transistor that works in a wide range of frequencies. It is very important to explain that have chosen a certain method of transformation which will be explained in detail later. This method can convert S, Y, and Z parameters for extracting the different parasitic elements. It will be also used the most important equations to calculate the parasitic elements on a transistor. The parasitic elements will be obtained from the different S, Y, and Z parameters depending on the type of parasitic element and frequency range.es_ES
dc.format.extent50 p.es_ES
dc.language.isoenges_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.subject.otherEM simulationses_ES
dc.subject.otherEquivalent circuites_ES
dc.subject.otherGaN HEMTes_ES
dc.subject.otherGatees_ES
dc.subject.otherHigh-frequencyes_ES
dc.subject.otherLayoutes_ES
dc.subject.otherParasitic elementses_ES
dc.subject.otherSmall-signales_ES
dc.subject.otherS-parameterses_ES
dc.subject.otherTransistores_ES
dc.titleOptimization and design of GaN HEMT layout and extraction of parasitic elementses_ES
dc.typeinfo:eu-repo/semantics/masterThesises_ES
dc.rights.accessRightsembargoedAccesses_ES
dc.description.degreeMáster en Ingeniería de Telecomunicaciónes_ES
dc.embargo.lift2027-07-23
dc.date.embargoEndDate2027-07-23


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Atribución-NoComercial-SinDerivadas 3.0 EspañaExcepto si se señala otra cosa, la licencia del ítem se describe como Atribución-NoComercial-SinDerivadas 3.0 España