Optimization and design of GaN HEMT layout and extraction of parasitic elements
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Identificadores
URI: http://hdl.handle.net/10902/25391Registro completo
Mostrar el registro completo DCAutoría
Telechea González, Héctor
Fecha
2022-07-22Director/es
Derechos
Atribución-NoComercial-SinDerivadas 3.0 España
Disponible después de
2027-07-23
Palabras clave
EM simulations
Equivalent circuit
GaN HEMT
Gate
High-frequency
Layout
Parasitic elements
Small-signal
S-parameters
Transistor
Resumen/Abstract
ABSTRACT: This project concerns the design and optimization of GaN HEMT. This optimization is going to be achieved by extracting the different parasitic elements that appear on a transistor. In this way, it is possible to reduce its effect and discover what are the advantages and disadvantages introduced for this type of parasitic elements. These parasitic elements are divided into two separate categories: intrinsic and extrinsic parasitic elements. It is going to be considered different modifications to the layout of the transistor, such as changing physical dimensions or removing /adding different parts. Therefore, it is going to observe the main differences between dissimilar layouts and layouts with/without one specific part. Another objective is to set a small signal equivalent circuit. This equivalent circuit can model the behavior of this type of transistor to know most of the lumped elements that are included on a GaN HEMT at low and high frequencies. That’s why is desirable to design a transistor that works in a wide range of frequencies. It is very important to explain that have chosen a certain method of transformation which will be explained in detail later. This method can convert S, Y, and Z parameters for extracting the different parasitic elements. It will be also used the most important equations to calculate the parasitic elements on a transistor. The parasitic elements will be obtained from the different S, Y, and Z parameters depending on the type of parasitic element and frequency range.