Improved noise immunity for two-sample PLL applicable to single-phase PFCs

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URI: http://hdl.handle.net/10902/23799
ISBN: 978-1-6654-3635-9
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Autoría
Lamo Anuarbe, Paula; Azcondo Sánchez, Francisco JavierAutoridad Unican; Pigazo López, AlbertoAutoridad Unican
Fecha
2021
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© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publicado en
IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL), Cartagena, Colombia, 2021
Editorial
Institute of Electrical and Electronics Engineers, Inc.
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Palabras clave
PLL
Synchronization
Noise immunity
Resumen/Abstract
Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC.
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