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dc.contributor.authorÁlvarez Ruiz, Ángel
dc.contributor.authorUgarte Olano, Íñigo 
dc.contributor.authorFernández Solórzano, Víctor Manuel 
dc.contributor.authorSánchez Espeso, Pablo Pedro 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2021-11-23T11:14:20Z
dc.date.available2021-11-23T11:14:20Z
dc.date.issued2019
dc.identifier.isbn978-1-7281-5458-9
dc.identifier.isbn978-1-7281-5459-6
dc.identifier.otherTEC2017-86722-C4-3-Res_ES
dc.identifier.urihttp://hdl.handle.net/10902/23133
dc.description.abstractIn the fields of high performance computing (HPC) and embedded systems, the current trend is to employ heterogeneous platforms which integrate general purpose CPUs with specialized accelerators such as GPUs and FPGAs. Programming these architectures to approach their theoretical performance limits is a complex issue. In this article, we present a design methodology targeting heterogeneous platforms which combines a novel dynamic offloading mechanism for OpenMP and a scheduling strategy for assigning tasks to accelerator devices. The current OpenMP offloading model depends on the compiler supporting each target device, with many architectures still unsupported by the most popular compilers, such as GCC and Clang. In our approach, the software and/or hardware design flows for programming the accelerators are dissociated from the host OpenMP compiler and the device-specific implementations are dynamically loaded at runtime. Moreover, the assignment of tasks to computing resources is dynamically evaluated at runtime, with the aim of maximizing performance when using the available resources. The proposed methodology has been applied to a video processing system as a test case. The results demonstrate the flexibility of the proposal by exploiting different heterogeneous platforms and design particularities of devices, leading to a significant performance improvement.es_ES
dc.description.sponsorshipThis work has been funded by FEDER/Ministerio de Ciencia, Innovación y Universidades – Agencia Estatal de Investigacion/TEC2017-86722-C4-3-R, also under the FitOptiVis Project (ECSEL2017-1-737451), which is funded by the EU (H2020) and Ministerio de Ciencia, Innovación y Universidades.es_ES
dc.format.extent6 p.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineers, Inc.es_ES
dc.rights© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.source34th Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, 2019, 168-173es_ES
dc.titleDesign space exploration in heterogeneous platforms using OpenMPes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/DCIS201949030.2019.8959934es_ES
dc.rights.accessRightsopenAccesses_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/H2020/783162/EU/From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems/FITOPTIVIS/es_ES
dc.identifier.DOI10.1109/DCIS201949030.2019.8959934
dc.type.versionacceptedVersiones_ES


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