Design space exploration in heterogeneous platforms using OpenMP
Ver/ Abrir
Identificadores
URI: http://hdl.handle.net/10902/23133ISBN: 978-1-7281-5458-9
ISBN: 978-1-7281-5459-6
Registro completo
Mostrar el registro completo DCAutoría
Álvarez Ruiz, Ángel; Ugarte Olano, Íñigo


Fecha
2019Derechos
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publicado en
34th Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, 2019, 168-173
Editorial
Institute of Electrical and Electronics Engineers, Inc.
Enlace a la publicación
Resumen/Abstract
In the fields of high performance computing (HPC) and embedded systems, the current trend is to employ heterogeneous platforms which integrate general purpose CPUs with specialized accelerators such as GPUs and FPGAs. Programming these architectures to approach their theoretical performance limits is a complex issue. In this article, we present a design methodology targeting heterogeneous platforms which combines a novel dynamic offloading mechanism for OpenMP and a scheduling strategy for assigning tasks to accelerator devices. The current OpenMP offloading model depends on the compiler supporting each target device, with many architectures still unsupported by the most popular compilers, such as GCC and Clang. In our approach, the software and/or hardware design flows for programming the accelerators are dissociated from the host OpenMP compiler and the device-specific implementations are dynamically loaded at runtime. Moreover, the assignment of tasks to computing resources is dynamically evaluated at runtime, with the aim of maximizing performance when using the available resources. The proposed methodology has been applied to a video processing system as a test case. The results demonstrate the flexibility of the proposal by exploiting different heterogeneous platforms and design particularities of devices, leading to a significant performance improvement.
Colecciones a las que pertenece
- D50 Congresos [464]
- D50 Proyectos de Investigación [404]