| dc.contributor.author | Lamo Anuarbe, Paula | |
| dc.contributor.author | Ruiz Robredo, Gustavo A. | |
| dc.contributor.author | Azcondo Sánchez, Francisco Javier | |
| dc.contributor.author | Pigazo López, Alberto | |
| dc.contributor.other | Universidad de Cantabria | es_ES |
| dc.date.accessioned | 2021-01-20T09:55:33Z | |
| dc.date.available | 2021-01-20T09:55:33Z | |
| dc.date.issued | 2020 | |
| dc.identifier.isbn | 978-1-7281-7160-9 | |
| dc.identifier.other | RTI2018-095138-BC31 | es_ES |
| dc.identifier.uri | http://hdl.handle.net/10902/20442 | |
| dc.description.abstract | A low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL) for application in low cost single-phase Power Factor Correction (PFC) converters is proposed. The design reduces the sampling rate of the grid voltage and replaces trigonometric functions by a digital oscillator and divisions by approximations, without reducing the 2S-PLL synchronization capability. The proposal is evaluated and validated with simulations and experimentally. | es_ES |
| dc.description.sponsorship | This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-BC31 PEGIA - Power Electronics for the Grid and Industry Applications. | es_ES |
| dc.format.extent | 5 p. | es_ES |
| dc.language.iso | eng | es_ES |
| dc.publisher | Institute of Electrical and Electronics Engineers, Inc. | es_ES |
| dc.rights | 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
| dc.source | IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL), Aalborg, Denmark, 2020 | es_ES |
| dc.subject.other | Phase Locked Loop | es_ES |
| dc.subject.other | Synchronization | es_ES |
| dc.subject.other | PLL | es_ES |
| dc.subject.other | Computational burden | es_ES |
| dc.subject.other | Low switching frequency | es_ES |
| dc.subject.other | Digital implementation | es_ES |
| dc.title | Implementation oriented two-sample phase locked loop for single-phase PFCs | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.relation.publisherVersion | https://doi.org/10.1109/COMPEL49091.2020.9265750 | es_ES |
| dc.rights.accessRights | openAccess | es_ES |
| dc.identifier.DOI | 10.1109/COMPEL49091.2020.9265750 | |
| dc.type.version | acceptedVersion | es_ES |
