Implementation oriented two-sample phase locked loop for single-phase PFCs

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Identificadores
URI: http://hdl.handle.net/10902/20442
ISBN: 978-1-7281-7160-9
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Autoría
Lamo Anuarbe, Paula; Ruiz Robredo, Gustavo A.Autoridad Unican; Azcondo Sánchez, Francisco JavierAutoridad Unican; Pigazo López, AlbertoAutoridad Unican
Fecha
2020
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2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publicado en
IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL), Aalborg, Denmark, 2020
Editorial
Institute of Electrical and Electronics Engineers, Inc.
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Palabras clave
Phase Locked Loop
Synchronization
PLL
Computational burden
Low switching frequency
Digital implementation
Resumen/Abstract
A low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL) for application in low cost single-phase Power Factor Correction (PFC) converters is proposed. The design reduces the sampling rate of the grid voltage and replaces trigonometric functions by a digital oscillator and divisions by approximations, without reducing the 2S-PLL synchronization capability. The proposal is evaluated and validated with simulations and experimentally.
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