Timed automata for modelling caches and pipelines

Cassez, Franck; González de Aledo Marugán, Pablo

doi:10.4204/EPTCS.196.4

dc.contributor.author	Cassez, Franck
dc.contributor.author	González de Aledo Marugán, Pablo
dc.contributor.other	Universidad de Cantabria	es_ES
dc.date.accessioned	2020-12-17T09:14:46Z
dc.date.available	2020-12-17T09:14:46Z
dc.date.issued	2015-11
dc.identifier.issn	2075-2180
dc.identifier.other	TEC2011-28666-C04-02	es_ES
dc.identifier.other	TEC2014-58036-C4-3-R	es_ES
dc.identifier.uri	http://hdl.handle.net/10902/20198
dc.description.abstract	In this paper, we focus on modelling the timing aspects of binary programs running on architectures featuring caches and pipelines. The objective is to obtain a timed automaton model to compute tight bounds for the worst-case execution time (WCET) of the programs using model-checking tehcniques.	es_ES
dc.description.sponsorship	Author gratefully acknowledges the funding from projects TEC2011-28666-C04-02, TEC2014-58036-C4-3-R and grant BES-2012-055572, awarded by the Spanish Ministry of Economy and Competitivity.	es_ES
dc.format.extent	9 p.	es_ES
dc.language.iso	eng	es_ES
dc.publisher	Open Publishing Association	es_ES
dc.rights	Attribution 4.0 International	es_ES
dc.rights.uri	http://creativecommons.org/licenses/by/4.0/	*
dc.source	Electronic Proceedings in Theoretical Computer Science, 2015, 196, 37-45	es_ES
dc.source	1st Workshop on Models for Formal Analysis of Real Systems (MARS), Suva, Fiji, 2015	es_ES
dc.title	Timed automata for modelling caches and pipelines	es_ES
dc.type	info:eu-repo/semantics/conferenceObject	es_ES
dc.rights.accessRights	openAccess	es_ES
dc.identifier.DOI	10.4204/EPTCS.196.4
dc.type.version	publishedVersion	es_ES