dc.contributor.author | Leyva-Santes, Neiel | |
dc.contributor.author | Pérez Gallardo, Iván | |
dc.contributor.author | Hernández-Calderón, César A. | |
dc.contributor.author | Vallejo Gutiérrez, Enrique | |
dc.contributor.author | Moretó, Miquel | |
dc.contributor.author | Beivide Palacio, Ramón | |
dc.contributor.author | Ramírez-Salinas, Marco A. | |
dc.contributor.author | Villa-Vargas, Luis A. | |
dc.contributor.other | Universidad de Cantabria | es_ES |
dc.date.accessioned | 2020-03-30T13:48:40Z | |
dc.date.available | 2020-03-30T13:48:40Z | |
dc.date.issued | 2019 | |
dc.identifier.issn | 1865-0929 | |
dc.identifier.uri | http://hdl.handle.net/10902/18431 | |
dc.description.abstract | Current compute-intensive applications largely exceed the resources of single-core processors. To face this problem, multi-core processors along with parallel computing techniques have become a solution to increase the computational performance. Likewise, multi-processors are fundamental to support new technologies and new science applications challenges. A specific objective of the Lagarto project developed at the National Polytechnic Institute of Mexico is to generate an ecosystem of high-performance processors for the industry and HPC in Mexico, supporting new technologies and scientific applications. This work presents the first approach of the Lagarto project to the design of multi-core processors and the research challenges to build an infrastructure that allows the flagship core of the Lagarto project to scale to multi- and many-cores. Using the OpenPiton platform with the Ariane RISC-V core, a functional tile has been built, integrating a Lagarto I core with memory coherence that executes atomic instructions, and a NoC that allows scaling the project to many-core versions. This work represents the initial state of the design of mexican multi-and many-cores processors. | es_ES |
dc.format.extent | 14 p. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Springer Verlag | es_ES |
dc.rights | © Springer. This is a post-peer-review, pre-copyedit version of an article published in Communications in Computer and Information Science. The final authenticated version is available online at: https://doi.org/10.1007/978-3-030-38043-4_20 | es_ES |
dc.source | CCIS, volume 1151, pp 237-248 | es_ES |
dc.subject.other | Multi- and Many -core | es_ES |
dc.subject.other | Multiprocessors RISC-V | es_ES |
dc.subject.other | Interconnection networks | es_ES |
dc.title | Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip | es_ES |
dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
dc.relation.publisherVersion | https://doi.org/10.1007/978-3-030-38043-4_20 | es_ES |
dc.rights.accessRights | openAccess | es_ES |
dc.type.version | acceptedVersion | es_ES |