Efficient FPGA mapping for filtering applied algorithms

Abstract

The aim of this project is to show how the way a specific design is mapped in a FPGA influences the performance and the usage of resources. Hence, it turns out to be relevant to optimize how this mapping is implemented in a FPGA so higher sampling frequencies and/or less use of resources can be obtained. In addition, FPGAs have suffer a great development in recent years with the inclusión of several features that have risen the potential of these devices, allowing its use for more computational-demanding applications, such as filtering. The present work is framed in the previously mentioned scenario for improving how of filtering algorithms are mapped into FPGAs, taking advantage of the novelties that these devices have incorporate. This work is supported by two main chapters addressing two different filtering algorithms and that serve as an example of how mapping modifications can be done: wave digital filters and radix-2k feedforward FFT. For each of these filtering algorithms, a different mapping or structural modification which optimizes the application to execute in a FPGA is suggested. Finally, numeric results are provided to show the convenience of these adaptations in terms of resource usage, operating frequency and power consumption.