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dc.contributor.authorSuárez Rodríguez, Almudena 
dc.contributor.authorRamírez Terán, Franco Ariel 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2018-04-16T14:39:28Z
dc.date.available2018-04-16T14:39:28Z
dc.date.issued2017
dc.identifier.isbn978-1-5090-6360-4
dc.identifier.isbn978-1-5090-6361-1
dc.identifier.otherTEC2014-60283-C3-1-Res_ES
dc.identifier.urihttp://hdl.handle.net/10902/13503
dc.description.abstractAn in-depth stability analysis of a typical non-Foster matching network is presented. The investigation is carried out at two levels: considering an ideal implementation of the negative impedance inverter (NIC) and using detailed circuit-level descriptions of all its active and passive components. The ideal NIC model will enable an analytical derivation of the characteristic system and the system poles, which will provide insight into the main instability mechanisms in these configurations. A good qualitative agreement is obtained with the circuit-level analyses, based on pole-zero identification and bifurcation detection methods. The impact of significant parameters, such as the biasing resistors or the value of the reactive component to be negated, is investigated in detail. A circuit-level methodology is proposed to obtain the stability boundaries and margins in an efficient and rigorous manner. For illustration, a non-Foster circuit based on a NIC has been manufactured and measured, obtaining very good agreement with the analysis results.es_ES
dc.description.sponsorshipThis work has been funded by the Spanish Government under contract TEC2014-60283-C3-1-R, the European Regional Development Fund (ERDF/FEDER) and the Parliament of Cantabria (12.JP02.64069). The authors would like to thank S. Pana, University of Cantabria, for her assistance with the manufacturing process.es_ES
dc.format.extent4 p.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rights© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.sourceIEEE MTT-S International Microwave Symposium (IMS), Honolulu, Hawai, 2017, 340-343es_ES
dc.subject.otherNon-Foster networkes_ES
dc.subject.otherStabilityes_ES
dc.subject.otherBifurcationes_ES
dc.titleCircuit-level stability and bifurcation analysis of non-foster circuitses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/MWSYM.2017.8059115es_ES
dc.rights.accessRightsopenAccesses_ES
dc.identifier.DOI10.1109/MWSYM.2017.8059115
dc.type.versionacceptedVersiones_ES


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