| dc.contributor.author | Lamo Anuarbe, Paula | |
| dc.contributor.author | López Vidal, Felipe | |
| dc.contributor.author | Pigazo López, Alberto | |
| dc.contributor.author | Azcondo Sánchez, Francisco Javier | |
| dc.contributor.other | Universidad de Cantabria | es_ES |
| dc.date.accessioned | 2018-01-12T14:12:10Z | |
| dc.date.available | 2018-01-12T14:12:10Z | |
| dc.date.issued | 2017 | |
| dc.identifier.isbn | 978-1-5090-5326-1 | |
| dc.identifier.isbn | 978-1-5090-5327-8 | |
| dc.identifier.other | TEC2014-52316-R | es_ES |
| dc.identifier.uri | http://hdl.handle.net/10902/12819 | |
| dc.description.abstract | A new implementation of the recently proposed fixed-frequency two-sample (2S) quadrature generation subsystem (QSG) digital Phase Locked Loop PLL, applicable to single-phase Power Factor Correction (PFC), is proposed. Its characteristics are high accuracy and low computational burden. The proposed PLL includes a frequency feedback loop to improve the synchronization under line frequency variations. Its performance within a digital controller of a current sensorless bridgeless PFC is evaluated by simulations and experimentally. The obtained results are compared with previously published PLLs in the literature. | es_ES |
| dc.description.sponsorship | This work has been supported by the Spanish Ministry of Economy and Competitiveness under grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices. | es_ES |
| dc.format.extent | 7 p. | es_ES |
| dc.language.iso | eng | es_ES |
| dc.publisher | IEEE | es_ES |
| dc.rights | © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
| dc.source | IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, California, 2017, 29-35 | es_ES |
| dc.subject.other | PLL | es_ES |
| dc.subject.other | Bridgeless | es_ES |
| dc.subject.other | Converter | es_ES |
| dc.subject.other | Sensorless | es_ES |
| dc.subject.other | Synchronization | es_ES |
| dc.subject.other | Computational burden | es_ES |
| dc.title | Two-sample PLL with improved frequency response applied to single-phase current sensorless bridgeless PFCs | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.relation.publisherVersion | https://doi.org/10.1109/COMPEL.2017.8013281 | es_ES |
| dc.rights.accessRights | openAccess | es_ES |
| dc.identifier.DOI | 10.1109/COMPEL.2017.8013281 | |
| dc.type.version | acceptedVersion | es_ES |
