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dc.contributor.authorLamo Anuarbe, Paula
dc.contributor.authorLópez Vidal, Felipe 
dc.contributor.authorPigazo López, Alberto 
dc.contributor.authorAzcondo Sánchez, Francisco Javier 
dc.contributor.otherUniversidad de Cantabriaes_ES
dc.date.accessioned2017-05-03T18:09:00Z
dc.date.available2017-05-03T18:09:00Z
dc.date.issued2016
dc.identifier.isbn978-1-5090-1816-1
dc.identifier.isbn978-1-5090-1815-4
dc.identifier.otherTEC2014-52316-Res_ES
dc.identifier.urihttp://hdl.handle.net/10902/10903
dc.description.abstractNew power factor correction (PFC) stages such as bridgeless converters and the associated current shaping techniques require grid synchronization to ensure unity Displacement Power Factor (DPF). Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The application of a secondary control path to reach faster and more robustly the proper operation point previously applied in single/three-phase PLLs in grid connected converters is here proposed for the current sensorless bridgeless PFCs. This work analyzes the performance of three single-phase T/4 PLL structures, first without secondary control path, and later with feedforward and feedback secondary control paths, both in simulation and experimentally, and evaluates their applicability to current sensorless digitally controlled single phase bridgeless PFCs based on the current rebuilding technique.es_ES
dc.description.sponsorshipThis work has been supported by the Spanish Ministry of Economy and Competitiveness under grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices.es_ES
dc.format.extent5 p.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.sourceIEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), Trondheim, Norway, 2016, 8-12es_ES
dc.subject.otherConverteres_ES
dc.subject.otherCurrent sensorlesses_ES
dc.subject.otherPLLes_ES
dc.subject.otherBridgelesses_ES
dc.subject.otherPower factor conversiones_ES
dc.subject.otherFPGAes_ES
dc.titlePerformance analysis of 1ϕ T/4 PLLs with secondary control path in current sensorless bridgeless PFCses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.relation.publisherVersionhttps://doi.org/10.1109/COMPEL.2016.7556657es_ES
dc.rights.accessRightsopenAccesses_ES
dc.identifier.DOI10.1109/COMPEL.2016.7556657
dc.type.versionacceptedVersiones_ES


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