@conference{10902/38565,
year = {2025},
url = {https://hdl.handle.net/10902/38565},
abstract = {This work presents a hardware-aware Neural Architecture Search (NAS) framework for video-based human action recognition, targeting real-time deployment on FPGAbased System-on-Chip (SoC) platforms. The proposed method explores a constrained search space of Convolutional Neural Network (CNN)-Recurrent Neural Network (RNN) architectures aligned with a hardware-software pipeline where CNNs are mapped to FPGA Deep Learning Processing Units (DPUs) and RNNs to embedded ARM cores. A reinforcement learning (RL)-based controller, guided by a position-based discounted reward strategy, progressively learns to generate architectures that emphasize high-impact design decisions. Experiments on the UCF101 dataset demonstrate that the proposed architectures achieve 81.07 % accuracy, among the highest reported for CNNRNN models relying exclusively on spatial information. The results validate the effectiveness of the proposed framework in driving hardware-compatible and performance-optimized architecture exploration.},
organization = {This work has been supported by Projects PID2023-148285OBC42 and PID2023-148285OB-C43, funded by the Spanish MICIU/AEI/10.13039/501100011033 and by FEDER, UE, as part of the OASIS project (Open AI-Driven stack for enhanced HPEC platforms in embedded systems).},
publisher = {Institute of Electrical and Electronics Engineers, Inc.},
publisher = {40th Conference on Design of Circuits and Integrated Systems, Santander, 2025, 150-155},
title = {Video action recognition in SoC FPGAs driven by neural architecture search},
author = {Suárez Plata, Daniel Nicolás and Hernández Fernández, Pedro and Fernández Solórzano, Víctor Manuel and Marrero Callicó, Gustavo},
}