@conference{10902/3353,
year = {2006},
month = {9},
url = {http://hdl.handle.net/10902/3353},
abstract = {A 10 GHz CMOS VCO design in 0.4μm SiGe technology
is presented in this paper, providing a good compromise
between power consumption, noise, tunning range and chip area.
This design is intended to be used in a frequency synthesizer for
the 5150-5250MHz band in a direct conversion system in which
would run at double frequency to avoid adverse effects such as
frequency pulling and LO leakage. The phase noise at 1-MHz
frequency offset from the carrier is below -109dBc/Hz, with a
maximum power consumption of 22.6mW. The tunning range
under the presented load conditions is about 6.3%, and the VCO
itself occupies an area of only 0.075mm2.},
publisher = {URSI 2006, XXI Simposium Nacional de la Unión Científica Internacional de Radio, Oviedo, p. 1304-1306},
title = {VCO CMOS de bajo ruido a 10 GHz en tecnología SiGe de 0.4μm},
author = {Pérez Serna, Ernesto and Herrera Guardado, Amparo},
}