@conference{10902/25066,
year = {2021},
url = {http://hdl.handle.net/10902/25066},
abstract = {The integration of many processing elements per die makes it more difficult to provide low latency in the Network-on-Chip (NoC). Multihop bypass proposals, such as SMART, attack this problem by allowing flits to skip multiple routers in the path in a single cycle, drastically reducing latency while preserving a regular tiled layout. However, multihop bypass routers are more complex and relatively different from traditional NoC routers, since they rely on global broadcast signals and global allocation mechanisms. Additionally, the maximum number of nodes that can be bypassed within a single cycle is limited by the Critical Path Delay (CPD) of the NoC. Hence, a practical multihop bypass mechanism must also minimize this delay.

To simplify the design of multihop bypass mechanisms, this work introduces PlugSMART, an open-source pluggable Verilog module that extends a traditional router to support multihop bypass. PlugSMART follows a black box approach, requiring minimal modifications from the original router. As an application of PlugSMART, we introduce ProSMART, a multihop bypass extension of the efficient NoC router ProNoC. ProSMART is evaluated using simulations, FPGA, and ASIC synthesis. Results show that it is more performant and requires significantly fewer resources than previous open-source designs. The comparison with OpenSMART++, the most recent state-of-the-art SMART-based NoC, shows up to a 50% reduction in both area and CPD. Overall, PlugSMART constitutes a simple alternative for fast and efficient upgrading of existing NoC routers, allowing to implement multihop bypass and significantly improve performance while preserving the original characteristics of the router design.},
organization = {This research was supported by the Spanish Ministry of Science and Innovation (FPI Grant BES2017-079971 and contracts PID2019-107255GB-C21 and PID2019-105660RB-C22 /AEI / 10.13039 / 5011000 11033) and by the Catalan Government (contracts 2017-SGR-1414). This work also received funding from the European Union Horizon 2020 research and innovation programme under grant agreements number 779877 (Mont-Blanc 2020), 826647 (EPI) and 946002 (MEEP). M. Moreto was also partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramón y Cajal fellowship No. RYC-2016-21104.},
publisher = {NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip: 2021 Proceeding, Association for Computing MachineryNew YorkNYUnited States, 2021},
title = {PlugSMART: a pluggable open-source module to implement multihop bypass in Networks-on-Chip},
author = {Monemi, Alireza and Pérez Gallardo, Iván and Neiel, Leyva and Vallejo Gutiérrez, Enrique and Beivide Palacio, Ramón and Moretó, Miquel},
}