@conference{10902/20442,
year = {2020},
url = {http://hdl.handle.net/10902/20442},
abstract = {A low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL) for application in low cost single-phase Power Factor Correction (PFC) converters is proposed. The design reduces the sampling rate of the grid voltage and replaces trigonometric functions by a digital oscillator and divisions by approximations, without reducing the 2S-PLL synchronization capability. The proposal is evaluated and validated with simulations and experimentally.},
organization = {This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-BC31 PEGIA - Power Electronics for the Grid and Industry Applications.},
publisher = {Institute of Electrical and Electronics Engineers, Inc.},
publisher = {IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL), Aalborg, Denmark, 2020},
title = {Implementation oriented two-sample phase locked loop for single-phase PFCs},
author = {Lamo Anuarbe, Paula and Ruiz Robredo, Gustavo A. and Azcondo Sánchez, Francisco Javier and Pigazo López, Alberto},
}